YASKAWA SGD7S-1R9D Product Manual page 405

12.5 Synchronization with Distributed Clocks
Example of PDO Data Exchange Timing in DC Mode
• DC Cycle Time = 1 ms, Input Shift Time = 500 μs
Master
Network
Slave
S0
• DC Cycle Time = 125 μs, Input Shift Time = 0 μs
Master
Network
Slave
S0
Inputs Latch
12-10
Master application task
Master user
shift time
U
Frame
Sync0
event
Shift time Calc and copy time
(1C33 hex: 03 = 500 μs) (62 μs)
Input delay
(500 μs)
Inputs Latch
Master application task
Master user
shift time
U
Frame
Sync0
event
Calc and copy time (62 μs)
Input delay (125 μs)
Master application task
Frame
Sync0 shift time
S0
Sync0
event
Cycle time (1C32 hex: 02 = 1 ms)
Cycle time
(1 ms)
Master application task
Frame
Sync0 shift time
S0
Sync0
event
Cycle time (1C32 hex: 02 = 125 μs)
Cycle time (125 μs)
Master application task
U
S0
Sync0
event
Calc and copy time
(62 μs)
Output delay
(125 μs)
Outputs Valid
Master application task
U
Frame
S0
Sync0
event
Calc and copy time (62 μs)
Output delay (125 μs)
U
Frame
S0
U
S0
Outputs Valid