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acknowledged. The processor fetches the vector number from the inter-
rupting device, classifying the reference as an interrupt acknowledge on the
address bus. If external logic requests automatic vectoring (via the AVEC
pin), the processor internally generates a vector number determined by the
interrupt level number. If external logic indicates a bus error, the interrupt
is considered spurious, and the generated vector number references the
spurious interrupt vector number.
2.6 M68000 SIGNAL DIFFERENCES
The MC68302 core supports two additional signals not visible on the standard
M68000: IPEND and RMC. The interrupt pending (IPEND) signal provides
information to the on-chip bus arbiter to assert the internal and external bus-
clear signals, thus supporting a low-latency interrupt mechanism. IPEND is
not visible externally. Asserted externally on read-modify-write cycles, the
RMC signal is typically used as a bus lock to insure integrity of instructions
using the read-modify-write operation. The RMC signal from the M68000
core is applied to the arbiter and can be programmed to prevent the arbiter
from issuing bus grants until the completion of an MC68000-core-initiated
read-modify-write cycle.
The MC68302 can be programmed to use the RMC signal to negate address
status(AS) at the end of the read portion of the cycle and assert AS at the
beginning of the write portion of the cycle.
Two M68000 signals are omitted from the MC68302: valid memory address
(VMA) and enable (E). The valid peripheral address (VPA) signal is retained,
but is only used on the MC68302 as AVEC to direct the core to use an auto-
vector during interrupt acknowledge cycles.
2.7 MC68302 IMP CONFIGURATION CONTROL
Four entries in the external M68000 exception vector table are used as ad-
dresses for internal system configuration registers. The first entry is the on-
chip peripheral base address register (BAR) entry; the second is the on-chip
system control register (SCR); the third and fourth entries are reserved for
future use. Refer to 3.8 SYSTEM CONTROL for the detailed description of
the SCR.
MOTOROLA
NOTE
These registers are internally reset only when a total system reset
occurs by the simultaneous assertion of RESET and HALT. The CS
lines are not asserted on accesses to these locations.
MC68302 USER'S MANUAL
2-13
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