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Chapter 2
Signal Descriptions
This chapter provides a pinout diagram and signal descriptions for the MPC180E security
processor.
2.1 Signal Descriptions
Table 2-1 groups pins by functionality.
Signal
Pin
name
locations
A[18:29]
62, 64, 66,
67, 68, 70,
72–75, 77,
78
D[0:31]
1, 2, 4, 6,
7, 9, 11,
12, 14, 17,
18, 20, 22,
24, 28–32,
34, 36, 37,
38, 87, 89,
90, 92, 94,
96, 98, 99
TS
53
R/W
54
BURST
55
CS
56
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 2-1. Pin Descriptions
Signal
type
Signal pins
I
Address: address bus from the processor core. These bits are decoded in
the EBI to produce the individual module select lines to the EUs. Note that
the processor address bus might be 32 bits wide, while the MPC180E
address bus is only 12 bits wide. An example mapping of the processor bus
to the MPC180E bus is shown later in the functional description.
msb = bit 0
lsb = bit 31
I/O
Data: bidirectional data bus. This bus is connected directly to the processor
core.
msb = bit 0
lsb = bit 31
I
Transfer Start: transfer start pin for control port. This signal is asserted by
the bus master to indicate the start of a bus cycle that transfers data to or
from the MPC180E.
I
Read/Write: read/write line
1 = read cycle
0 = write cycle
I
Burst Transaction: active low signal that indicates when the current
read/write is a burst transfer.
I
Chip Select: active low signal that indicates when a data transfer is in
intended for the MPC180E. This is used by the MPC180E along with TS,
R/W, and A to begin a transfer.
Chapter 2. Signal Descriptions
Description
2-1
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