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•
Nap mode sequence
-
Set nap bit (HIDO[9]
=
1), clear doze and sleep bits (HIDO[8] and HIDO[lO]
=
0)
-
MPC750 asserts quiesce request (QREQ) signal
-
System asserts quiesce acknowledge (QACK) signal
-
MPC750 enters sleep mode after several processor clocks
•
Nap mode bus snoop sequence
-
System deasserts QACK signal for eight or more bus clock cycles
-
MPC750 snoops address tenure(s) on bus
-
System asserts QACK signal to restore full nap mode
•
Several methods of returning to full-power mode
-
Assert INT, SMI, MCP, decrementer, performance monitor, or thermal
management interrupts
-
Assert hard reset or soft reset
•
Transition to full-power takes no more than a few processor cycles
•
PLL and DLL running and locked to SYSCLK
10.2.1.5 Sleep Mode
Sleep mode consumes the least amount of power of the four modes since all functional units
are disabled. To conserve the maximum amount of power, the PLL may be disabled by
placing the PLL_CFG signals in the PLL bypass mode, and disabling SYSCLK. Note that
forcing the SYSCLK signal into a static state does not disable the MPC750's PLL, which
will continue to operate internally at an undefined frequency unless placed in PLL bypass
mode. Additionally, if the PLL is not disabled, the L2 cache interface DLL will remain
locked and the L2CLK_OUTA and L2CLK_OUTB signals will remain active. The DLL is
disabled by clearing the L2CR[L2E] bit to
O.
Due to the fully static design of the MPC750, internal processor state is preserved when no
internal clock is present. Because the time base and decrementer are disabled while the
MPC750 is in sleep mode, the MPC750's time base contents will have to be updated from
an external time base after exiting sleep mode if maintaining an accurate time-of-day is
required. Before entering the sleep mode, the MPC750 asserts the QREQ signal to indicate
that it is ready to disable bus snooping. When the system has ensured that snooping is no
longer necessary, it asserts QACK and the MPC750 will enter sleep mode.
•
All functional units disabled (including bus snooping and time base)
•
All nonessential input receivers disabled
-
Internal clock regenerators disabled
-
PLL and DLL still running (see below)
10-4
MPC750 RISC Microprocessor User's Manual
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