Indexed Addressing Modes - Motorola HC12 Refrence Manual

3.8 Indexed Addressing Modes

The CPU12 uses redefined versions of M68HC11 indexed modes that reduce execu-
tion time and eliminate code size penalties for using the Y index register. In most
cases, CPU12 code size for indexed operations is the same or is smaller than that for
the M68HC11. Execution time is shorter in all cases. Execution time improvements are
due to both a reduced number of cycles for all indexed instructions and to faster sys-
tem clock speed.
The indexed addressing scheme uses a postbyte plus 0, 1, or 2 extension bytes after
the instruction opcode. The postbyte and extensions do the following tasks:
1. Specify which index register is used.
2. Determine whether a value in an accumulator is used as an offset.
3. Enable automatic pre or post increment or decrement.
4. Specify size of increment or decrement.
5. Specify use of 5-, 9-, or 16-bit signed offsets.
This approach eliminates the differences between X and Y register use while dramat-
ically enhancing the indexed addressing capabilities.
Major advantages of the CPU12 indexed addressing scheme are:
• The stack pointer can be used as an index register in all indexed operations.
• The program counter can be used as an index register in all but autoincrement
and autodecrement modes.
• A, B, or D accumulators can be used for accumulator offsets.
• Automatic pre- or post-increment or pre- or post-decrement by –8 to +8
• A choice of 5-, 9-, or 16-bit signed constant offsets.
• Use of two new indexed-indirect modes.
— Indexed-indirect mode with 16-bit offset
— Indexed-indirect mode with accumulator D offset
Table 3-2 is a summary of indexed addressing mode capabilities and a description of
postbyte encoding. The postbyte is noted as xb in instruction descriptions. Detailed
descriptions of the indexed addressing mode variations follow the table.
All indexed addressing modes use a 16-bit CPU register and additional information to
create an effective address. In most cases the effective address specifies the memory
location affected by the operation. In some variations of indexed addressing, the ef-
fective address specifies the location of a value that points to the memory location af-
fected by the operation.
Indexed addressing mode instructions use a postbyte to specify X, Y, SP, or PC as the
base index register and to further classify the way the effective address is formed. A
special group of instructions (LEAS, LEAX, and LEAY) cause this calculated effective
address to be loaded into an index register for further calculations.
CPU12
REFERENCE MANUAL
ADDRESSING MODES MOTOROLA
3-5