Out-Of-Band (Oob) Signaling; 1-Byte Or 2-Byte Fabric Interface Width; Loopback; Crc - Xilinx Virtex-4 RocketIO User Manual

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Out-of-Band (OOB) Signaling

Out-of-band signaling is said to occur when TXP and TXN are driven to a common-mode
voltage indicating "electrical idle" for protocols such as PCI-Express and Serial ATA. The
TXENOOB and RXSIGDET behavior is represented in the following way in digital
simulation:
•
•

1-Byte or 2-Byte Fabric Interface Width

When using 1-byte or 2-byte fabric interface width, the upper 2,3,4 or 3,4 bytes respectively
appear to contain data. This behavior is inherent in the functionality of the Virtex-4
RocketIO transceiver.
Refer to

Loopback

In case of a pre-driver serial loopback or external cable loopback, RXRESET and TXRESET
must not be tied together; this causes the clock on the receive side to drift, resulting in
incorrect data. It is advisable never to tie the resets together. For pre-driver serial loopback,
TXPOST_TAP_PD must be set to FALSE, even for simulation.

CRC

•
•
Table 7-2: CRC Latency and CRCCLOCKDOUBLE Attribute
•
Refer to

Toggling GSR

The global set/reset (GSR) is a global routing of nets present in the design that provide a
means of setting or resetting applicable components in the device during configuration.
The simulation behavior of this signals is modeled using the glbl module in Verilog and
the ROC/ROCBUF components in VHDL.
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
When TXENOOB=0, normal data is transmitted on the TXP/TXN pins. When
TXENOOB=1, TXP/TXN pins are set at logic 1.
When logic 1 is detected on the RXP/RXN pins, RXSIGDET is set to 1. When normal
data is received on the RXP/RXN pins, RXSIGDET is set to 0.
Table 3-3, page 105 and
The CRC blocks of the MGT do not recognize start-of-frame (SOF/SOP) or end-of-
frame (EOF/EOP), and CRC errors are not indicated. These functions must be
implemented in the FPGA fabric.
CRC Latency is defined in
CRCCLOCKDOUBLE State
FALSE
TRUE
If CRCCLOCKDOUBLE = FALSE then the latency between CRCIN and CRCOUT is
4 cycles. If the CRCCLOCKDOUBLE = TRUE then the latency is 3 cycles
Chapter 5, "Cyclic Redundancy Check (CRC)"
www.xilinx.com
SmartModel Simulation Considerations
Figure 3-5, page 106 for details.
Table 7-2.
CRCIN → CRCOUT Latency
4 cycles
3 cycles
for further details.
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