Mdio Register Interface; Management Data Clock; Management Data Input/Output; Management Data Interrupt - Broadcom BCM5722 Programmer's Manual

BCM5722 Programmer's Guide
10/15/07
MDIO R I
EGISTER NTERFACE
The following figure shows the MDI register interface.
MAC Sublayer
Physical Layer
Mgmnt
MDC
Control
Mgmnt
Mgmnt Mgmnt
MDIO
Control
I/O I/O
(MII & GMII)
MDINT
MDI
Register
block

Figure 20: MDI Register Interface

Management Data Clock

The Management Data Clock (MDC) is driven by the MAC sublayer. The PHY will sink this signal to synchronize data transfer
on the MDIO signal—MDC is a reference clock. This clock is not functionally associated to either RX_CLK or TX_CLK. The
minimum period for this clock is 400 ns with high and low times having 160 ns duration.

Management Data Input/Output

The Management Data Input/Output (MDIO) signal passes control and status data, between the MAC and PHY sublayers.
MDIO is a bidirectional signal, meaning both the PHY and MAC may transfer data. The MAC typically transfers control
information and polls status; whereas, the PHY transfers status back to the MAC, using MDIO.

Management Data Interrupt

The integrated Broadcom PHY may be programmed to generate interrupts. A PHY status change initiates a Management
Data Interrupt (MDINT). A MDI mask register allows host software to selectively enable/disable status types, which cause
MDINT notification. The PHY will assert INTR until software clears the interrupt. Reading the status register will clear the
interrupt.

Management Register Block

The layout and configuration of MDI register block is device dependent. The MDI register block is the control/status access
point, which host software may read/write. The IEEE 802.3 specification defines a basic register block for MII and GMII; the
basic register set contains control and status registers. GMII also exposes an extended register set, used in 1000 Mbps
configuration/status. The fundamental point is to understand that the MDC and MDIO signals are used to access the MDI
register block.
Bro adco m C orp or atio n
Page 39 PHY Control Document 5722-PG101-R