BCM5722
MSI FIFO A
CCESS
The MSI FIFO Access Register is used to give an MSI request to the PCI block. The actual MSI data is indicated in the
bottom bits. If the MSI is properly enqueued into the FIFO, the overflow bit remains cleared. If the FIFO overflowed, the bit
is set and must be written to be cleared. If the overflow bit is set when the access register is written, no MSI is enqueued.
Bit
Field
31:4
Reserved
3
Overflow
2:0
MSI Data
Page 331
Message Signaled Interrupt Registers
R
(O
EGISTER
FFSET
Table 339: MSI FIFO Access Register (Offset 0x6008)
Description
Always 0.
No space left in FIFO.
Indicates which of the (up to eight) MSIs to use.
Bro adco m C orp or atio n
0
6008)
X
Programmer's Guide
10/15/07
Init
Access
0
RO
0
W2C
0
W/O
Document 5722-PG101-R
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