Figure 15: Smbus Transaction Phases; Figure 16: Smb_Clock Period (Master Mode) - Broadcom BCM5722 Programmer's Manual

BCM5722
SMBus Clock
The BCM5722 Ethernet controller's SMBus interface supports clock stretching. Slave devices may clock low to extend the
SMB_CLK signal, and the BCM5722 Ethernet controller absorbs the stretch latency. The programmer should refer to section
4.3.3 of the SMBus 2.0 manual for further details on this technology. The BCM5722 Ethernet controller maintains a minimum
compliant frequency of 10 KHz when clock is low extending.
The BCM5722 Ethernet controller's clock period (master mode) is 11 µs—a 90.9-KHz frequency. The SMB_CLK signal is
driven low T for 5 µs. The BCM5722 Ethernet controller floats the SMB_CLK high T
Low
SMB_CLK is driven low again. The low and high times are not guaranteed symmetric, since the rise may vary due to external
pull-up resistors or current sources. The rise time T
500 ns, but also may vary. See
SMB_CLK
E
VENTS
The SMB Attention bit and the five timeout bits in the ASF Control register are all ORed together to form a single ASF_ATTN
signal. Depending on the value of the ASF Attention Location field, this signal may then be mapped into one of several bit
positions in the RX CPU Event or TX CPU Event registers.
Page 31 System Management Bus
Start
3 Read/Write
1
Condition
2 Slave Address
0 2 8 10
4 Acknowledge

Figure 15: SMBus Transaction Phases

on SMB_CLK will vary from 300 ns to 1 µs. The fall time T
R
Figure 16.
500 ns
T
F
T
Low
5 µs

Figure 16: SMB_CLOCK Period (Master Mode)

Bro adco m C orp or atio n
Stop
5 Data Byte
7
Condition
18 20
6 Acknowledge
300 ns–1 µs
T
R
T
High,Max
6 µs
Programmer's Guide
for a maximum of 6 µs before the
High
F
Document 5722-PG101-R
10/15/07
is roughly