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Broadcom BCM5722 Programmer's Manual

Host programmer interface specification for the netxtreme and netlink family of highly integrated media access controllers

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Programmer's Guide

BCM5722

Host Programmer Interface Specification for the

NetXtreme® and NetLink™ Family of Highly

Integrated Media Access Controllers

5722-PG101-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203

10/15/07

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Page 1 Programmer’s Guide BCM5722 Host Programmer Interface Specification for the NetXtreme® and NetLink™ Family of Highly Integrated Media Access Controllers 5722-PG101-R 5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 10/15/07...
Page 2 , the Connecting everything logo, NetXtreme , and NetLink™ are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners.
Page 3: Table Of Contents
BCM5755 and BCM5755M MACs ........................ 9 Typical Application ..........................10 BCM5754, BCM5754M, BCM5787, and BCM5787M MACs ..............11 Typical Application ..........................12 Programming the BCM5722 Ethernet Controllers................... 13 Section 3: Hardware Architecture ..................14 Theory of Operation ........................... 14 Receive Data Path ............................15 RX Engine.............................
Page 4 BCM5722 Programmer’s Guide 10/15/07 Data SDI............................21 Method 1 ..........................21 Method 2 ..........................21 Method Selection........................21 RXMAC Time-sync .........................21 Data/ISO Mixed Transmit Packet Traffic Example .................22 DMA Read..............................25 Read Engine............................25 Read FIFO.............................25 Buffer Manager............................25 DMA Write..............................26 Write Engine ............................26 Write FIFO .............................26 Buffer Manager............................26...
Page 5 Programmer’s Guide BCM5722 10/15/07 GMII Block ............................37 MDIO Register Interface ........................39 Management Data Clock ....................... 39 Management Data Input/Output ....................39 Management Data Interrupt ......................39 Management Register Block......................39 Self-Test ..............................40 BIST ..............................40 JTAG..............................40 Section 4: NVRAM Configuration ..................
Page 6 BCM5722 Programmer’s Guide 10/15/07 Section 6: Receive Data Flow................... 59 Introduction..............................59 Receive Producer Ring ..........................61 Setup of Producer Rings using RCBs ....................61 Receive Producer Ring RCB—Register offset 0x2450–0x245f .............61 Other Considerations Relating to Producer Ring Setup............61 RCB Setup Pseudo Code.......................62 Receive Buffer Descriptors........................62...
Page 7 Programmer’s Guide BCM5722 10/15/07 Section 7: Transmit Data Flow..................74 Introduction ..............................74 Send Rings ..............................74 Ring Control Block ..........................75 Host-Based Send Ring ......................... 76 Checksum Offload ............................. 77 Scatter/Gather ............................78 VLAN Tag Insertion ............................ 79 TX Data Flow Diagram ..........................79 Section 8: Device Control ....................
Page 8 Memory Mapped I/O Registers......................129 PCI Command Register .......................129 PCI State Register........................129 PCI Base Address Register......................130 Register Quick Cross Reference ......................131 BCM5722 Family..........................131 Pseudocode............................132 Memory Window Read in Standard Mode..................132 Memory Window Write in Standard Mode..................132 Register Read in Standard Mode ....................132 Register Write in Standard Mode ....................132...
Page 9 Programmer’s Guide BCM5722 10/15/07 Operational Characteristics......................... 134 Read/Write DMA Engines ......................134 Register Quick Cross Reference ......................135 Expansion ROM............................135 Description ............................135 Operational Characteristics......................... 135 BIOS ..............................136 Preboot Execution Environment ....................136 Power Management ..........................136 Description ............................136 Operational Characteristics.........................
Page 10 Word Swap Non-Frame Data = 1 and Byte Swap Non-Frame Data = 1........151 Section 10: Ethernet Link Configuration............... 152 Overview..............................152 GMII/MII ..............................152 Configuring the BCM5722 Ethernet controller for GMII and MII Modes ..........152 Link Status Change Indications ......................153 Configuring the GMII/MII PHY ......................153 Reading a PHY Register ......................153 Writing a PHY Register ........................154...
Page 11 Clear Ticks on BD Events Mode ......................185 No Interrupt on Force Update ......................185 No Interrupt on DMAD Force ......................185 Section 12: BCM5722 Ethernet Controller Register Definitions........186 PCI Configuration Registers ........................186 Vendor ID Register (Offset 0x00)......................189 Device ID Register (Offset 0x02) ......................
Page 12 VPD Next Capabilities Pointer Register (Offset 0x51).................200 VPD Flag and Address Register (Offset 0x52)..................200 VPD Data Register (Offset 0x54) ......................201 Broadcom Vendor-Specific Capabilities ....................202 Vendor-Specific Capability ID Register (Offset 0x58)................202 Vendor-Specific Next Capabilities Pointer Register (Offset 0x59)............202 Reset Counters Register (Offset 0x5C)....................202...
Page 13 Programmer’s Guide BCM5722 10/15/07 Device Serial No Upper DW Override Register (Offset: 0x64)............203 Miscellaneous Host Control Register (Offset 0x68) ................204 DMA Read/Write Control Register (Offset 0x6C)................205 PCI State Register (Offset 0x70) ......................206 PCI Clock Control Register (Offset 0x74) ................... 207 Register Base Address Register (Offset 0x78) ...................
Page 14 BCM5722 Programmer’s Guide 10/15/07 PCIe-Enhanced Capabilities ........................224 Advanced Error Reporting Enhanced Capability Header Register (Offset 0x100) ......224 Uncorrectable Error Status Register (Offset 0x104)................224 Uncorrectable Error Mask Register (Offset 0x108) ................225 Uncorrectable Error Severity Register (Offset 0x10C) ................226 Correctable Error Status Register (Offset 0x110)................227 Correctable Error Mask Register (Offset 0x114) .................227...
Page 15 Programmer’s Guide BCM5722 10/15/07 Receive BD Standard Producer Ring Index Register (Offset 0x268–0x26F)........239 Receive BD Return Ring 1 Consumer Index Register (Offset 0x284–0x287)........239 Receive BD Return Ring 2 Consumer Index Register (Offset 0x28C–0x28F)........239 Receive BD Return Ring 3 Consumer Index Register (Offset 0x294–0x297)........239 Receive BD Return Ring 4 Consumer Index Register (Offset 0x29C–0x29F)........
Page 16 BCM5722 Programmer’s Guide 10/15/07 Indirection Table Registers 1–14 for Entry 8–119 (Offset: 0x634–0x66B) ..........261 Indirection Table Register 15 (Offset: 0x66C) ..................262 Hash Key Register 0 (Offset: 0x670)....................262 Hash Key Register 1–8 (Offset: 0x674–0x693) ...................262 Hash Key Register 9 (Offset: 0x694)....................263 Receive MAC Programmable IPv6 Extension Header Register (0x6A0) ..........263...
Page 17 (Offset 0x08B4) ..................... 267 etherStatsUndersizePkts (0x08B8)....................267 Send Data Initiator Control Registers ....................268 Send Data Initiator Mode Register (Offset 0x0C00)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787, and BCM5906 Only............... 269 Send Data Initiator Mode Register (Offset 0x0C00)—BCM5907 Only..........269 Send Data Initiator Status Register (Offset 0x0C04) ................
Page 18 Receive BD Initiator Status Register (Offset 0x2C04).................289 Receive BD Initiator Local NIC Receive BD Producer Index Register (Offset 0x2C0C–0x2C0F)..290 Standard Receive BD Producer Ring Replenish Threshold Register (Offset 0x2C18–0x2C1B)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only ..............................290 Standard Receive BD Producer Ring Replenish Threshold Register (Offset 0x2C18–0x2C1B)—BCM5906 Only ....................290...
Page 19 Flow Attention Register (Offset 0x3C48) .................... 297 NIC Receive BD Consumer Index Register (Offset 0x3C54–0x3C57) ..........298 NIC Diagnostic Return Rings Producer Index Registers 1–4 (Offset 0x3C80–0x3C8F)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only........298 NIC Diagnostic Return Rings Producer Index Register (Offset 0x3C80–0x3C83)—BCM5906 Only.. 299 NIC Diagnostic Send BD Consumer Index Register (Offset 0x3CC0–0x3CC3) .........
Page 20 BCM5722 Programmer’s Guide 10/15/07 BM Hardware Diagnostic 3 Register (Offset 0x4454)................310 Receive Flow Threshold Register (Offset 0x4458)................310 Read DMA Control Registers........................311 Read DMA Mode Register (Offset 0x4800)..................311 Read DMA Status Register (Offset 0x4804)..................313 Read DMA Programmable IPv6 Extension Header Register (Offset: 0x4808) ........313 Write DMA Control Registers ........................314...
Page 21 Programmer’s Guide BCM5722 10/15/07 RXMBUF Cluster Free Enqueue Register (Offset 0x5CC8) ............... 328 RDIQ FTQ Write/Peek Register (Offset 0x5CFC)................328 Message Signaled Interrupt Registers ....................330 MSI Mode Register (Offset 0x6000) ....................330 MSI Status Register (Offset 0x6004) ....................330 MSI FIFO Access Register (Offset 0x6008)..................
Page 22 BCM5722 Programmer’s Guide 10/15/07 SMBus Output Register (Offset 0x6C08) ....................358 ASF Watchdog Timer Register (Offset 0x6C0C).................359 ASF Heartbeat Timer Register (Offset 0x6C10)..................359 Poll ASF Timer Register (Offset 0x6C14)....................360 Poll Legacy Timer Register (Offset 0x6C18) ..................360 Retransmission Timer Register (Offset 0x6C1C) ................360 Time Stamp Counter Register (Offset 0x6C20)...................360...
Page 23 Programmer’s Guide BCM5722 10/15/07 NVM Arbitration Watchdog Timer Register (Offset 0x702C)............... 376 NVM Auto-Sense Status Register (0x7038h) ..................377 BIST Registers............................378 BIST Control Register (Offset 0x7400) ....................378 BIST Status Register (Offset 0x7404)....................378 BIST Status Register (Offset 0x7404)....................379 PCIe Registers ............................
Page 24 BCM5722 Programmer’s Guide 10/15/07 Data Link Status Register (Offset 0x7D04) ..................397 Data Link Attention Register (Offset 0x7D08) ..................398 Data Link Attention Mask Register (Offset 0x7D0C) ................398 Next Transmit Sequence Number Debug Register (Offset 0x7D10)...........399 ACKed Transmit Sequence Number Debug Register (Offset 0x7D14)..........399 Purged Transmit Sequence Number Debug Register (Offset 0x7D18)..........399...
Page 25 Programmer’s Guide BCM5722 10/15/07 PHY Hardware Diagnostic 1 Register (Offset 0x7E38)............... 412 PHY Hardware Diagnostic 2 Register (Offset 0x7E3C) ..............413 Transceiver Registers..........................414 MII Control Register (PHY_Addr = 0x1, Reg_Addr = 00h)..............415 MII Status Register (PHY_Addr = 0x1, Reg_Addr = 01h) ..............416 PHY Identifier Register (PHY_Addr = 0x1, Reg_Addresses 02h)............
Page 26 BCM5722 Programmer’s Guide 10/15/07 In Phase ............................438 MULTICOLOR[2] Multicolor Selector ...................438 MULTICOLOR[1] Multicolor Selector ...................438 Expansion Register 05h: Multicolor LED Flash Rate Controls ............438 Alternation Rate..........................439 Flash Rate ............................439 Expansion Register 06h: Multicolor LED Programmable Blink Controls ..........439 Blink Update Now.........................439 Blink Rate .............................439...
Page 27 Programmer’s Guide BCM5722 10/15/07 Link LED Mode ..........................455 Clock Alignment Control (PHY_Addr = 0x1, Reg_Addr = 1Ch, Shadow 00011b) ......456 Write Enable ..........................456 Shadow Register Selector ......................456 GTXCLK Clock Delay Enable ...................... 456 Spare Control 2 (PHY_Addr = 0x1, Reg_Addr = 1Ch, Shadow 00100b)..........457 Write Enable ..........................
Page 28 BCM5722 Programmer’s Guide 10/15/07 Sleep Timer Select ........................462 Wakeup Timer Select ........................463 LED Selector 1 (PHY_Addr = 0x1, Reg_Addr = 1Ch, Shadow 01101b) ..........463 Write Enable..........................464 Shadow Register Selector......................464 LED2 Selector ..........................464 LED1 Selector ..........................464 LED Selector 2 (PHY_Addr = 0x1, Reg_Addr = 1Ch, Shadow 01110b) ..........465 Write Enable..........................465...
Page 29 Programmer’s Guide BCM5722 10/15/07 Auxiliary 1000BASE-X Control (PHY_Addr = 0x1, Reg_Addr = 1Ch, Shadow 11011b)..... 470 Write Enable ..........................470 Shadow Register Selector ......................470 Use SerDes Mode Counters ......................470 Disable Remote Fault Sensing ....................470 Comma Detect Enable......................... 470 FIFO Elasticity ..........................
Page 30 BCM5722 Programmer’s Guide 10/15/07 SerDes LED Mode ........................475 SerDes Auto Power Down mode....................476 Power Down Inactive Interface.....................476 Autodetect Media Default ......................476 Autodetect Media Priority ......................476 Autodetect Media Enable ......................476 Mode Control (PHY_Addr = 0x1, Reg_Addr = 1Ch, Shadow 11111b)..........477 Write Enable..........................477 Shadow Register Selector......................477...
Page 31 Programmer’s Guide BCM5722 10/15/07 100BASE-TX Capability....................... 486 10BASE-T FDX Capability ....................486 10BASE-T Capability ......................486 MF Preamble Suppression ....................486 Auto-Negotiation Complete....................487 Auto-Negotiation Capability ....................487 Link Status ........................... 487 Jabber Detect........................487 Extended Capability ......................487 PHY Identifier Registers ......................487 Auto-Negotiation Advertisement Register..................
Page 32 BCM5722 Programmer’s Guide 10/15/07 Toggle ..........................491 Message Code Field ......................491 Unformatted Code Field .......................491 Auto-negotiation Link Partner (LP) Next Page Transmit Register..........492 Next Page..........................492 Message Page ........................492 Acknowledge 2 ........................492 Toggle ..........................492 Message Code Field ......................492 Unformatted Code Field .......................492 100BASE-X Auxiliary Control Register..................493...
Page 33 Programmer’s Guide BCM5722 10/15/07 SMII Slow RXD ........................496 Auxiliary Control/Status Register ....................497 Jabber Disable ........................497 Link Disable ......................... 497 HSQ:LSQ ..........................498 Edge Rate [1:0] ........................498 Auto-Negotiation Indicator ....................498 Force100/10 Indication ......................498 Speed Indication ........................498 Full-Duplex Indication ......................
Page 34 Auto-Negotiation Complete ....................507 Acknowledge Complete......................508 Acknowledge Detected......................508 Ability Detect ........................508 Super Isolate ........................508 10BASE-T Serial Mode ......................508 Broadcom Test Register.......................508 Shadow Register Enable......................508 Shadow Register Detailed Description ....................509 Miscellaneous Control Register (Shadow Register)..............509 Forced Auto-MDIX Enable ....................509 Auto-Negotiation Hardware Override ...................509 Auxiliary Status 2 Register (Shadow Register) ................509...
Page 35 Programmer’s Guide BCM5722 10/15/07 Noise[7:0]..........................511 FIFO Consumption[3:0]......................511 Auxiliary Mode 3 Register (Shadow Register) ................512 FIFO Size Select [3:0]......................512 Auxiliary Status 4 Register (Shadow Register) ................512 Packet Length Counter [15:0] ....................512 Appendix A: Flow Control....................513 Notes .................................
Page 36 BCM5722 Programmer’s Guide 10/15/07 IST OF IGURES Figure 1: Typical BCM5755-Based NIC Board Block Diagram ...............10 Figure 2: Typical BCM5754-Based NIC Board Block Diagram ...............12 Figure 3: Functional Block Diagram ........................14 Figure 4: Receive Data Path ...........................15 Figure 5: Transmit Data Path ..........................17 Figure 6: ISO SBD Internal Block Diagram .....................19...
Page 37 Figure 46: Standard Mode Memory Window ....................121 Figure 47: Flat Mode Memory Map......................... 123 Figure 48: Flat Mode Memory Map......................... 127 Figure 49: Techniques for Accessing BCM5722 Ethernet Controller Local Memory........128 Figure 50: PCI Command Register......................... 129 Figure 51: PCI Base Address Register ......................130 Figure 52: PCI Base Address Register Bits Read in Standard Mode .............
Page 38 BCM5722 Programmer’s Guide 10/15/07 Figure 69: File Transfer Scenario: Speed Mismatch ..................514 Figure 70: File Transfer Scenario: Speed Buffers Run Low................515 Figure 71: File Transfer Scenario: Switch Backpressure ................516 Figure 72: File Transfer Scenario: Switch Flow Control ..................516 Figure 73: File Transfer Scenario: File Transfer Complete ................517 Figure 74: Pause Control Frame ........................517...
Page 39 Programmer’s Guide BCM5722 10/15/07 IST OF ABLES Table 1: Pseudocode............................2 Table 2: Family Features............................ 6 Table 3: Family Revision Levels......................... 8 Table 4: BCM5755 NIC Part Component Breakdown ..................10 Table 5: BCM5754 NIC Part Component Breakdown ..................12 Table 6: ISO SDI Block.............................
Page 40 Table 35: Recommended BCM5722 Ethernet controller Memory Pool Watermark Settings......85 Table 36: Recommended BCM5722 Ethernet controller Low Watermark Maximum Receive Frames’ Settings..............................85 Table 37: Recommended BCM5722 Ethernet controller Standard Ring Initialization Settings for Internal Memory Only ..............................86 Table 38: Recommended BCM5722 Ethernet Controller Host Coalescing Tick Counter Settings ....88 Table 39: Recommended BCM5722 Ethernet Controller Host Coalescing Frame Counter Settings ....88...
Page 41 Table 51: PCI -X Registers..........................135 Table 52: GPIO Usage for BCM5700/BCM5701 Power Management for Broadcom Drivers ......139 Table 53: GPIO Usage for BCM5703C/BCM5703S and Later Power Management for Broadcom Drivers... 139 Table 54: BCM5722 Ethernet controller Power Pins ..................139 Table 55: Power Management Registers .......................
Page 42 BCM5722 Programmer’s Guide 10/15/07 Table 75: Required Memory Regions for WOL Pattern ..................160 Table 76: 10/100 Mbps Mode Frame Patterns Memory .................163 Table 77: Frame Control Field for 10/100 Mbps Mode ...................164 Table 78: Example of Splitting 10/100 Mbps Frame Data in Pattern Data Structure ........164 Table 79: Firmware Mailbox Initialization ......................165...
Page 43 Programmer’s Guide BCM5722 10/15/07 Table 110: Maximum Latency Register (Offset 0x3F) ..................196 Table 111: Power Management Capability Register (Offset 0x48) ..............197 Table 112: PM Next Capabilities Pointer Register (Offset 0x49)..............197 Table 113: Power Management Capabilities Register (Offset 0x4A) ............. 197 Table 114: Power Management Control/Status Register (Offset 0x4C)............
Page 44 BCM5722 Programmer’s Guide 10/15/07 Table 145: Device Control Register (Offset 0xD8)..................217 Table 146: Device Status Register (Offset 0xDA)...................218 Table 147: Link Capabilities Register (Offset 0xDC)..................219 Table 148: Link Control Register (Offset 0xE0) ....................220 Table 149: Link Status Command Register (Offset 0xE2) ................220 Table 150: MSI Capability ID Register (Offset 0xE8)..................221...
Page 45 Table 185: PCIe 1.1 Advisory Non-Fatal Error Masking (Offset: 0x18C) ............237 Table 186: High-Priority Mailbox Registers ....................238 Table 187: High-Priority Mailbox Structure..................... 238 Table 188: Ethernet MAC Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, Bro adco m Co rp or atio n Document...
Page 46 BCM5722 Programmer’s Guide 10/15/07 BCM5754, BCM5787 Only ......................241 Table 189: Ethernet MAC Control Registers—BCM5906 Only...............243 Table 190: Ethernet MAC Mode Register (Offset 0x400) ................245 Table 191: Ethernet MAC Status Register (Offset 0x404) ................246 Table 192: Ethernet MAC Event Enable Register (Offset 0x408) ..............247 Table 193: LED Control Register (Offset 0x40C)....................247...
Page 47 BCM5722 10/15/07 Table 222: Statistics Registers ........................264 Table 223: Send Data Initiator Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only......................268 Table 224: Send Data Initiator Control Registers—BCM5906 Only ............... 268 Table 225: Send Data Initiator Mode Register (Offset 0x0C00)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only...............
Page 48 Table 274: Receive Data Initiator Mode Register (Offset 0x2C00) ..............289 Table 275: Receive BD Initiator Status Register (Offset 0x2C04) ..............289 Table 276: Standard Receive BD Producer Ring Replenish Threshold Register (Offset 0x2C18)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only ........290 Table 277: Standard Receive BD Producer Ring Replenish Threshold Register (Offset 0x2C18)—BCM5906...
Page 49 BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only....298 Table 288: NIC Return Ring Producer Index Register (Offset 0x3C80)—BCM5906 Only ......299 Table 289: NIC Send BD Consumer Index (Offset 0x3CC0)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only.................... 300 Table 290: NIC Send BD Consumer Index (Offset 0x3CC0)—BCM5906 Only..........300 Table 291: Memory Arbiter Registers......................
Page 50 Table 305: BM Hardware Diagnostic 3 Register (Offset 0x4454) ..............310 Table 306: Receive Flow Threshold Register (Offset 0x4458) ...............310 Table 307: Read DMA Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only ......................311 Table 308: Read DMA Control Registers—BCM5906 Only................311 Table 309: Read DMA Mode Register (Offset 0x4800) ..................311...
Page 51 Table 352: Serial EEPROM Control Register (Offset 0x6840) ............... 341 Table 353: MDI Control Register (Offset 0x6844) ..................342 Table 354: RX CPU Event Enable Register (Offset 0x684C)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only.................... 343 Table 355: RX CPU Event Enable Register (Offset 0x684C)—BCM5906 Only ..........344 Table 356: Wake-on-LAN Registers.......................
Page 52 BCM5722 Programmer’s Guide 10/15/07 BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only ....347 Table 361: Miscellaneous Cable Sense Control Register (Offset: 0x6890)—BCM5906 Only ......347 Table 362: Fast Boot Program Counter Register (Offset 0x6894) ..............348 Table 363: Chip Mode Register (Offset: 0x6898) ...................349 Table 364: Energy Detect Timer Register (Offset: 0x689C) ................350...
Page 53 Programmer’s Guide BCM5722 10/15/07 Table 395: NVM Command Register (Offset 0x7000)..................370 Table 396: NVM Status Register (0x7004H) ....................370 Table 397: NVM Write Register (Offset 0x7008) .................... 371 Table 398: NVM Address Register (Offset 0x700C)..................371 Table 399: NVM Read Register (Offset 0x7010).................... 371 Table 400: NVM Config 1 Register (Offset 0x7014) ..................
Page 54 BCM5722 Programmer’s Guide 10/15/07 Table 430: DMA Completion Header Diagnostic Register 2 (Offset 0x7C4C) ..........392 Table 431: DMA Completion Misc. Diagnostic Register (Offset 0x7C50) ............392 Table 432: DMA Completion Misc. Diagnostic Register (Offset 0x7C54) ............393 Table 433: DMA Completion Misc. Diagnostic Register (Offset 0x7C58) ............393...
Page 55 Programmer’s Guide BCM5722 10/15/07 0x7C5C) ............................393 Table 435: Split Controller Misc 0 Register Diagnostic Register (Offset 0x7C60).......... 394 Table 436: Split Controller Misc 1 Register Diagnostic Register (Offset 0x7C64).......... 394 Table 437: TLP Status Register (Offset 0x7C60) ................... 394 Table 438: TLP Status Register (Offset 0x7C60) ...................
Page 56 BCM5722 Programmer’s Guide 10/15/07 Table 469: PHY Receive Error Counter (Offset 0x7E20)................408 Table 470: PHY Receive Framing Error Counter (Offset 0x7E24)..............408 Table 471: PHY Receive Error Threshold Register (Offset 0x7E28) ..............409 Table 472: PHY Test Control Register (Offset 0x7E2C) .................409 Table 473: PHY/SerDes Control Override Register (Offset 0x7E30)..............411...
Page 57 Programmer’s Guide BCM5722 10/15/07 Table 504: Expansion Register 10h: Cable Diagnostic Controls..............440 Table 505: Expansion Register 11h: Cable Diagnostic Results ..............441 Table 506: Expansion Register 12h: Cable Diagnostic Lengths Channels1/2 ..........442 Table 507: Expansion Register 13h: Cable Diagnostic Lengths Channels 3/4 ..........443 Table 508: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 000, Normal)....
Page 58 BCM5722 Programmer’s Guide 10/15/07 Power Control)..........................447 Table 511: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 100, Misc Test 1) ..448 Table 512: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 111, Misc Control)..449 Table 513: Auxiliary Status Summary Register (PHY_Addr = 0x1, Reg_Addr = 19h) ........450...
Page 59 Table 556: Auxiliary Mode Register (Address 29d, 1Dh) ................506 Table 557: Auxiliary Multiple PHY Register (Address 30d, 1Eh)..............507 Table 558: Broadcom Test Register (Address 31d, 1Fh) ................508 Table 559: Miscellaneous Control Register (Shadow Register 16d, 10h) ............509 Table 560: Auxiliary Status 2 Register (Shadow Register 27d, 1Bh) .............
Page 60: Section 1: About This Document
BCM5906 and BCM5906M NetLink This document focuses on the registers, control blocks, and software interfaces necessary for host software programming. This document is intended to complement the data sheet for the appropriate member of the BCM5722 Ethernet controllers. The errata documentation (see “Revision Levels”...
Page 61: Notational Conventions
This document generally avoids referencing bits by offset; the register definition section provides register and bit offsets. UNCTIONAL VERVIEW Functional descriptions provide high level overviews of the BCM5722 architectural blocks. The black box inputs/outputs from block diagrams aid software developers with programming the device. PERATIONAL HARACTERISTICS This section describes how software programs or interfaces with a hardware block.
Page 62 BCM5722 Programmer’s Guide 10/15/07 Table 1: Pseudocode (Cont.) Definition Notation Notes <Block> Begin or Cstyle { Any valid logic including <Expression>, <Repetition>, <While>, <Conditionals>, <Pseudo Code> <Assignment>, etc. End or Cstyle} <While> While <expression> Other variants of while valid (i.e., Do while, and so <Block>...
Page 63: Related Documents
Programmer’s Guide BCM5722 10/15/07 ELATED OCUMENTS Refer to the following Broadcom documents for additional information on the BCM5722 Ethernet controllers: ® • BCM57XX NetXtreme Programmer’s Guide: Programming details for the BCM5700, BCM5701, BCM5702, BCM5703, BCM5704, BCM5705, BCM5721, BCM5751, BCM5752, BCM5714, and BCM5715 BCM57XX devices •...
Page 64: Section 2: Introduction
S e c t i on 2 : In t ro du c t i o n NTRODUCTION The BCM5722 NetXtreme and NetLink family of Media Access Controller (MAC) devices are highly-integrated, single-chip gigabit Ethernet LAN controller solutions for high-performance network applications. The above devices integrate the following major functions to provide a single-chip solution for gigabit LAN-on-motherboard (LOM) and network interface card (NIC) applications.
Page 65: Feature Comparison
BCM5722 Programmer’s Guide 10/15/07 EATURE OMPARISON The following table shows the feature matrix of BCM5722 Ethernet controllers covered in this document. Table 2: Family Features Feature BCM5722 BCM5754 BCM5755 BCM5755M BCM5756M BCM5757 BCM5786 BCM5787 BCM5787M BCM5754M BCM5906 BCM5906M Data Management VLAN tag support (IEEE 802.1Q)
Page 66 Programmer’s Guide BCM5722 10/15/07 Table 2: Family Features (Cont.) Feature BCM5722 BCM5754 BCM5755 BCM5755M BCM5756M BCM5757 BCM5786 BCM5787 BCM5787M BCM5754M BCM5906 BCM5906M Host Bus Interfaces PCIe v1.1 x1 bus interface LAN Interfaces 10/100/1000BASE-T full-duplex/half-duplex BCM5722 10/100 only 10/100 only Ethernet controller...
Page 67: Revision Levels
BCM5722 Ethernet controllers. Host software can use the PCI Revision ID and Chip ID information in the PCI configuration registers to determine the revision level of the BCM5722 Ethernet controller on the board, and then load the appropriate workaround described in the errata sheets.
Page 68: Bcm5755 And Bcm5755M Macs
BCM5722 Programmer’s Guide 10/15/07 BCM5755 BCM5755M MAC The BCM5755/BCM5755M are seventh-generation 10/100/1000BASE-T Ethernet LAN controller solutions for high- performance network applications. The devices combine a triple-speed IEEE 802.3-compliant MAC with a triple-speed Ethernet transceiver, a x1 PCIe bus interface, and on-chip buffer memory in a single device. Following are important features of BCM5755 and BCM5755M devices.
Page 69: Typical Application
Programmer’s Guide BCM5722 10/15/07 YPICAL PPLICATION Figure 1 shows a typical BCM5755-based NIC board layout. 1000BASE-T Link Status LED 100BASE-T Link Status LED 10BASE-T Link Status LED 25-MHz Activity LED Crystal PNP for 1.2V Regulator Magnetic BCM5755 MEDIA RJ-45 64-KB Serial EEPROM or Flash...
Page 70: Bcm5754, Bcm5754M, Bcm5787, And Bcm5787M Macs
BCM5722 Programmer’s Guide 10/15/07 BCM5754, BCM5754M, BCM5787, BCM5787M MAC The BCM5754/BCM5754M/BCM5787/BCM5787M are seventh-generation 10/100/1000BASE-T Ethernet LAN controller solutions for high-performance network applications. The devices combine a triple-speed IEEE 802.3-compliant MAC with a triple-speed Ethernet transceiver, a x1 PCIe bus interface, and on-chip buffer memory in a single device. Following are important features of BCM5754, BCM5754M, BCM5787 and BCM5787M devices.
Page 71: Typical Application
Programmer’s Guide BCM5722 10/15/07 YPICAL PPLICATION Figure 2 shows a typical BCM5754-based NIC board layout. 1000BASE-T Link Status LED 100BASE-T Link Status LED 10BASE-T Link Status LED 25-MHz Activity LED Crystal PNP for 1.2V Regulator Magnetic BCM5754 MEDIA RJ-45 64-KB Serial EEPROM or Flash...
Page 72: Programming The Bcm5722 Ethernet Controllers
BCM5722 Ethernet controllers. Host software can use the PCI Revision ID and Chip ID information in the PCI configuration registers to determine the revision level of the BCM5722 Ethernet controller on the board, and then load the appropriate workarounds described in the errata sheets.
Page 73: Section 3: Hardware Architecture
PERATION Figure 3 shows the major functional blocks and interfaces of the BCM5722 Ethernet controllers. There are two packet flows: MAC-transmit and receive. The device’s DMA engine bus-masters packets from host memory to device local storage, and vice-versa. The host bus interface is compliant with PCIe standards. The RX MAC moves packets from the integrated PHY into device internal memory.
Page 74: Receive Data Path
BCM5722 Programmer’s Guide 10/15/07 ECEIVE RX E NGINE The receive engine (see Figure 4) activates whenever a packet arrives from the PHY. Host RX Producer Ring NIC RX Producer Ring Host RX Empty BD Return Rings List Placement List Initiator...
Page 75: Rules Checker
Programmer’s Guide BCM5722 10/15/07 ULES HECKER The rules checker examines frames. After a frame has been examined, the appropriate classification bits are set in the buffer descriptor. The rules checker is part of the RX data path and the frames are classified during data movement to NIC memory.
Page 76: Transmit Data Path
BCM5722 Programmer’s Guide 10/15/07 RANSMIT TX MAC The Read DMA engine moves packets from host memory into internal NIC memory (see Figure 5). When the entire packet is available, the transmit MAC is activated. Host Send Producer Rings NIC Send Ring Cache...
Page 77: Isochronous Send Ring (Bcm5906, Bcm5906M Only)
Programmer’s Guide BCM5722 10/15/07 (BCM5906, BCM5906M SOCHRONOUS ONLY In addition to the normal (or best-effort) data send ring (known as the Data SBD), a second send ring, the isochronous (ISO) send ring (known as the ISO SBD), is available on the BCM5906/BCM5906M. The ISO SBD supports Residential Ethernet applications such as Voice Over IP (VOIP) and video streaming, and offers the following features: •...
Page 78: Internal Block Diagram
BCM5722 Programmer’s Guide 10/15/07 Internal Block Diagram ISO SBD non-empty Data SBD non-empty SDI = Send Data Initiator ISO SDI Data SDI Network Clock Network clock > launch time RDMA TXMAC RXMAC Figure 6: ISO SBD Internal Block Diagram ISO SDI The ISO SDI block implements a 32-bit network time clock that counts in ns.
Page 79: Figure 7: Time-Sync Packet
Programmer’s Guide BCM5722 10/15/07 Table 6: ISO SDI Block Offset Host Address – 0x00 – – 0x04 Flags 0x08 Launch Time VLAN tag 0x0C Bit 10 in the Flags field of the ISO SBD notifies the transmit MAC to transmit the frame as a time sync packet, which is...
Page 80 BCM5722 Programmer’s Guide 10/15/07 Data SDI The isochronous packet is sensitive to the latency delay from the ISO SDI to the TXMAC. This means that the flow control of the normal data traffic must be carefully handled in order not to queue up too many normal data packets ahead of an ISO packet in TXMBUF memory.
Page 81: Figure 8: Sample Traffic Flow With Iso And Normal Data Packets
Programmer’s Guide BCM5722 10/15/07 Data/ISO Mixed Transmit Packet Traffic Example Figure 8 illustrates a sample traffic flow scenario of a mixture of isochronous packets and normal data best-effort traffic packets. ISO SBD Ring 64 Bytes 125us 64 Bytes 125us 64 Bytes...
Page 82: Table 7: Bcm5906 Status Block
BCM5722 Programmer’s Guide 10/15/07 Table 7: BCM5906 Status Block Offset 0x00 Status Word – 0x04 Unused – 0x08 Receive Standard Consumer Index Unused 0x0C Unused – 0x10 Data Send BD Consumer Index Receive Return BD Producer Index 0x14 ISO Send BD Consumer Index Unused •...
Page 83: Table 9: Example Of Setting Up An Iso Stream
Programmer’s Guide BCM5722 10/15/07 • Register 0xc28 fields are defined as follows: 0xc28[31:2] is the timestamp field. 0xc28[1:0] is the timestamp flags field. Bit 0 is the tx time-sync packet timestamp valid bit, and bit 1 is the rx time- sync packet timestamp valid bit.
Page 84: Figure 9: Dma Read Engine
BCM5722 Programmer’s Guide 10/15/07 DMA R NGINE The DMA read engine (see Figure 9) activates whenever a host read is initiated by the send or receive data paths. Buffer Manager Host Send Buffer Descriptors NIC BD BD Packet#1 text BD Packet#1...
Page 85: Figure 10: Dma Write Engine
Programmer’s Guide BCM5722 10/15/07 DMA W RITE RITE NGINE The DMA write engine (see the following figure) activates whenever a host write is initiated by the send or receive data paths. Host Receive Buffer Frame Descriptor Ring BD Memory Cracker...
Page 86: Figure 11: Asf System Architecture
BCM5722 Programmer’s Guide 10/15/07 YSTEM ANAGEMENT Figure 11 shows the architecture of the SMBus and the location of the ASF in the system. Cat5 RJ45 Filter Four Rx/Tx Pairs SMB_Clock pin BCM57XX (ASF Enabled) Vbus Remote Alert ASF Legacy Alert...
Page 87 Programmer’s Guide BCM5722 10/15/07 VERVIEW The System Management block of the NetXtreme devices contains all of the hardware necessary to support a implementation of the ASF protocol primarily in firmware. This hardware includes six dedicated timers, a low-level SMBus 2.0-compliant interface, registers for driving the SMBus interface, and a global control and event register. The system management block can also be used to support additional (non-ASF) management technologies such as IPMI.
Page 88: Figure 12: Smbus Start And Stop Conditions
3.3V and 5.0V PCI signaling application. The SMBus signals are exempt from a few requirements regarding loading and pull-ups, and the programmer is encouraged to read the ECN on the PCI SIIG website. The BCM5722 Ethernet controller’s SMBus interface meets the high power requirements stated in the SMBus 2.2 specification.
Page 89: Figure 13: Two Masters Arbitrate For Smbus
Programmer’s Guide BCM5722 10/15/07 START SMBDATA Float High by Master1 SMBCLK Master1 Quiesces—Arbitration Loss SMBDATA (MASTER1) Master2 Continues Transaction SMBDATA (MASTER2) SMBDATA Sampled Low by Master1 (Master1 backs off SMBus) Both Masters Sample SMBDATA High (Both Masters Continue) Figure 13: Two Masters Arbitrate for SMBus...
Page 90: Figure 15: Smbus Transaction Phases
SMB_CLK signal, and the BCM5722 Ethernet controller absorbs the stretch latency. The programmer should refer to section 4.3.3 of the SMBus 2.0 manual for further details on this technology. The BCM5722 Ethernet controller maintains a minimum compliant frequency of 10 KHz when clock is low extending.
Page 91 LED C ONTROL The BCM5722 Ethernet controller supports four LEDs—one for data traffic in either direction and three for 10/100/1000 Mbps links established. The traffic LED blinks during transmit and receive data movement through the device. The blink rate is programmable with a default of approximately 15 Hz.
Page 92: Figure 17: Host Coalescing Engine
The Host Coalescing Engine is responsible for pacing the rate at which the NIC updates the send and receive ring indices located in host memory space. The completion of a NIC update is reflected through an interrupt on the BCM5722 Ethernet controller INTA pin or a Message Signalled Interrupt (MSI).
Page 93 Programmer’s Guide BCM5722 10/15/07 A host update occurs whenever one of the following criteria is met: • The number of BDs consumed for frames received, without updating receive indices on the host, is equal to or has exceeded the threshold set in the Receive_Max_Coalesced_BD register (see “Receive Max Coalesced BD Count...
Page 94 MDI crossover capability are connected, an algorithm determines which end performs the crossover function. During 1000BASE-T operation, the BCM5722 Ethernet controllers swap the transmit symbols on pairs 0 and 1 and pairs 2 and 3 if auto-negotiation completes in the MDI crossover state. The 1000BASE-T receiver automatically detects pair swaps on the receive inputs and aligns the symbols properly within the decoder.
Page 95: Figure 18: Media Independent Interface
Link Partner when downgrade is active, as shown by a 1 in bit 14 of MII register 11h. PHY C ONTROL The BCM5722 Ethernet controller supports the following physical layer interfaces: • The MII is used in conjunction with 10-/100-Mbps copper Ethernet transceivers.
Page 96: Gmii Block
BCM5722 Programmer’s Guide 10/15/07 The specifics of MII may be located in section 22 of the IEEE 802.3 specification. RXD[3:0] are the receive data signals; TXD[3:0] are the transmit data signals. MII operates at both 10-Mbps and 100-Mbps wire-speeds. (Gigabit Ethernet uses the GMII standard.) When MAC and PHY are configured for 10 Mbps operation, the RX_CLK1 and MII_TXCLK clocks run...
Page 97: Figure 19: Gmii Block
Programmer’s Guide BCM5722 10/15/07 Pulse Amplitude Modulated Symbol (PAM5) encoding is leveraged for Gigabit Ethernet wire transmissions. PAM5 uses five encoding levels: -2, -1, 0, 1, and 2. Four symbols are transmitted in parallel on the four twisted-wire pairs. The four symbols create a code group (an eight-bit octet).
Page 98: Mdio Register Interface
PHY transfers status back to the MAC, using MDIO. Management Data Interrupt The integrated Broadcom PHY may be programmed to generate interrupts. A PHY status change initiates a Management Data Interrupt (MDINT). A MDI mask register allows host software to selectively enable/disable status types, which cause MDINT notification.
Page 99: Self-Test
The standard packaging for the NetXtreme family does not provide pinout for JTAG. An industry standard BSDL definition of the JTAG implementation is available from Broadcom Technical Support. Bro adco m Co rp or atio n...
Page 100: Section 4: Nvram Configuration
All configuration settings are default-configured in the official release binary image files provided in Broadcom's CD software releases. However, the settings chosen as default by Broadcom may not be what best suits a particular OEM's application, so some settings may need to be changed by the OEM.
Page 101: Section 5: Common Data Structures
Programmer’s Guide BCM5722 10/15/07 Se ction 5: Com mon Da ta Str uc t ur es HEORY OF PERATION Several device data structures are common to the receive, transmit, and interrupt processing routines. These data structures are hardware-related and are used by device drivers to read and update state information.
Page 102: Producer And Consumer Indices
BCM5722 Programmer’s Guide 10/15/07 RODUCER AND ONSUMER NDICES The Producer Index and the Consumer Index control which descriptors are valid for a given ring. Each ring will have its own separate Producer and Consumer Indices. When incremented, the Producer Index can be used to add elements to the ring.
Page 103: Ring Control Blocks
Programmer’s Guide BCM5722 10/15/07 ONTROL LOCKS Each ring (send or receive) has a Ring Control Block (RCB) associated with it. Each RCB has the format shown in Table Table 10: Ring Control Block Format Offset (bytes) 16 15 0x00 Host Ring Address...
Page 104: Figure 22: Transmit Ring Data Structure Architecture Diagram
BCM5722 Programmer’s Guide 10/15/07 Transmit Ring Data Scructure is located in the host (as shown below), and the device will keep a local (not shown) copy of the rings. Rings and buffer descriptors would be solely located in on-chip memory space.
Page 105: Send Buffer Descriptors
Programmer’s Guide BCM5722 10/15/07 Send Buffer Descriptors The format of an individual send buffer descriptor is shown in Table Table 12: Send Buffer Descriptors Format Offset (Bytes) 16 15 0x00 Host Address [63:0] 0x04 0x08 Length [15:0] Flags [15] HdrLen [7:5] Flags [11:0]...
Page 106: Receive Rings
Note: The BCM5722 Ethernet controller does not validate the value of the Length field and may generate an error on the PCI bus if the Length field has a value of 0. The host driver must ensure that the Length field is nonzero before enqueueing the BD onto the Send Ring.
Page 107: Figure 23: Receive Return Ring Memory Architecture Diagram
Programmer’s Guide BCM5722 10/15/07 Receive Buffer Descriptor Host Address index type flags ip chksum tcp_udp_chsum error flag vlan tag Ring Control Block reserve Host Memory opaque Receive Ring #1 Host Ring Address max_len flags Host Buffer Prod NIC Ring Address...
Page 108: Receive Producer Ring
BCM5722 Programmer’s Guide 10/15/07 Receive Producer Ring The receive producer ring resides in the host and points to empty host receive buffers that will later be filled with received packet data. The controller will internally cache a copy of the producer ring. When the host software driver has a free host receive packet buffer available for incoming packets, it will fill out a receive buffer descriptor and have that descriptor point to the available buffer.
Page 109: Receive Buffer Descriptors
Programmer’s Guide BCM5722 10/15/07 Receive Buffer Descriptors The format of Standard Receive Buffer Descriptors (in both producer ring and return rings) is shown in Table Table 15: Receive Descriptors Format Offset (bytes) 16 15 0x00 Host Address 0x04 0x08 Index...
Page 110 BCM5722 Programmer’s Guide 10/15/07 Table 16: Defined Flags for Receive Buffers (Cont.) Bits Name Description RSS Hash Type (BCM5755 Indicates the hash type used in RSS hash calculation for a received packet. and BCM5755M only) VLAN_TAG* If set to 1 in a return ring, it indicates that the packet associated with this buffer contained a four-byte IEEE 802.1Q VLAN tag.
Page 111: Table 17: Defined Error Flags For Receive Buffers
Programmer’s Guide BCM5722 10/15/07 Table 17: Defined Error Flags for Receive Buffers Bits Name Description 31:9 Reserved Should be set to 0. GIANT_PKT_RCVD If set to 1, the received packet was longer than the maximum packet length value set in the Receive MTU Size register (see “Receive MTU Size Register (Offset 0x43C)”...
Page 112: Status Block
BCM5722 Programmer’s Guide 10/15/07 TATUS LOCK The Status Block is another shared memory data structure that is located in host memory. The Status Block is 20 bytes in length. Host software will need to allocate 20 bytes of non-paged memory space for the Status Block and set the Status Block Host Address register to point to the host memory physical address reserved for this structure.
Page 113: Table 19: Status Block Format For Bcm5755 And Bcm5755M Devices
Programmer’s Guide BCM5722 10/15/07 The BCM5755 and BCM5755M devices support four Receive Return Rings. The Status Block format for these devices is given below. Table 19: Status Block Format for BCM5755 and BCM5755M Devices Offset 16 15 0x00 Status Word...
Page 114 BCM5722 Programmer’s Guide 10/15/07 The Status Block format for these devices is given below. • The Status Tag field contains an unique eight-bit tag value in bits 7:0 when the Status Tagged Status Mode bit of the Miscellaneous Host Control register (see “Miscellaneous Host Control Register (Offset 0x68)”...
Page 115: Device Statistics
Programmer’s Guide BCM5722 10/15/07 EVICE TATISTICS MAC S TATISTICS “Statistics Registers” on page 264 for the MAC statistics supported by the devices. MIB N ETWORK NTERFACE TATISTICS Host Interrupts The statistics shown in Table 21 are maintained by the send data initiator engine.
Page 116: Dma Resources
BCM5722 Programmer’s Guide 10/15/07 DMA Resources These statistics are generated by FTQ for monitoring any state machine which adds DMA descriptors to the either DMA engine. These state machines include the: • Send BD initiator • Receive BD initiator •...
Page 117: Class Of Service Statistics
Programmer’s Guide BCM5722 10/15/07 Class of Service Statistics The class of service statistics shown in Table 28 are generated by the Send Data Initiator state machine. Table 28: Send Data Initiator Class of Service Statistics Value Name Description COSIfHCOutPkts (Offset 0xC80–0xC83) Number of frames sent from send ring.
Page 118 BCM5722 Programmer’s Guide 10/15/07 S e c t i o n 6 : R e c e i v e D a t a Fl ow NTRODUCTION The RX MAC pulls BDs from RX producer rings. The RX BD specifies the location(s) in host memory where packet data may be moved.
Page 119: Figure 24: Receive Buffer Descriptor Cycle
Programmer’s Guide BCM5722 10/15/07 Standard Producer Ring Device Driver DMA Read RX Return Packet Engine Host Interrupt Protocol Interface List Local Rx MAC Coalescing Service (i.e. TCP/IP) Initiator Memory Engine Routine RX Indicate DMA Write Engine Available Return Ring 1...
Page 120 (“Receive MAC Mode Register (Offset 0x468)” on page 254). If the Accept Oversized bit (bit 5) of this register is set, the BCM5722 Ethernet controller accepts packets (of size up to 64 KB) larger than the size specified in the MTU.
Page 121: Figure 25: Receive Producer Ring Rcb Setup
64-bit memory address and may be in any memory alignment and may point to any byte boundary. For performance and CPU efficiency reasons, it is recommended that memory be cache-aligned. The BCM5722 Ethernet controller supports cache line sizes of 8, 16, 32, 64, 128, 256, and 512 bytes. The cache line size value is important for the controller to determine when to use the PCI memory write and invalidate command.
Page 122 The host software manages the producer rings through the Mailbox registers and by using the status block. It does this by writing to the Mail Box registers when a BD is available to DMA to the BCM5722 Ethernet controller and reading the status block to see how many BDs have been consumed by the BCM5722 Ethernet controller.
Page 123: Figure 26: Mailbox Registers
The Receive Producer Ring Producer Index register contains the index value of the next buffer descriptor from the producer ring that is available for DMA to the BCM5722 Ethernet controller from the host. When the host software updates the Receive Producer Ring Producer Index, the BCM5722 Ethernet controller is automatically signaled that a new BD is waiting for DMA.
Page 124 (SSRAM) at offset 0x200 (this region should not be confused with the register space in the chip). The RCB max_len field is used to indicate the number of buffer descriptor entries in a return ring. If an invalid value is set, the BCM5722 Ethernet controller indicates an attention error in the Flow Attention register.
Page 125: Table 32: Receive Bd Rules Control Register
RAME LASSIFICATION The BCM5722 Ethernet controller has a feature that allows for the classification of receive packets based on a set of rules. The rules are determined by the host software and then input into the BCM5722 Ethernet controller. A packet can be accepted or rejected based on the rules initialized into two rules register areas. The packets can also be classified into groups of packets of higher to lower priority using the rules registers.
Page 126: Table 33: Receive Bd Rules Value/Mask Register
BCM5722 Programmer’s Guide 10/15/07 Name Description Default Enable. Enabled if set to 1 – & And With Next. This rule and next must both be true to match. The class fields – must be the same. A disabled next rule is considered true. Processor activation bits are specified in the first rule in a series.
Page 127: Figure 27: Class Of Service Example
HECKSUM ALCULATION Whether the host software NOS supports checksum offload or not, the BCM5722 Ethernet controller automatically calculates the IP, TCP, and UDP of received packets as described in RFC 791, RFC 793, and RFC 768, respectively. Which protocol checksum value is produced can be determined by reading the status flag field in the Receive Return Ring.
Page 128: Table 34: Frame Format With 802.1Q Vlan Tag Inserted
In the Receive MAC Mode register (offset 0x468–0x46b), the Keep VLAN Tag Diag Mode bit (bit 10) can be set to force the BCM5722 Ethernet controller to not strip the VLAN tag from the packet. This is only for diagnostic purposes.
Page 129: Figure 28: Overview Diagram Of Rx Flow
1. The host software updates a Receive Producer Ring Index in the Mailbox registers. 2. A receive BD or series of BDs with the corresponding index is DMAed to the BCM5722 Ethernet controller from the host- based Receive Producer Ring.
Page 130 BCM5722 Ethernet controller automatically DMAs the BD to itself from the host. When the DMA is completed, the BCM5722 Ethernet controller (as the consumer) updates the status block’s receive consumer ring index to signal it successfully consumed the BD. The BCM5722 Ethernet controller keeps this BD in internal memory to know where to put a packet that is received from the network.
Page 131: Figure 29: Rss Receive Processing Sequence
Programmer’s Guide BCM5722 10/15/07 Base CPU Number Indirection Table Masked Hash Result Result Hash Hash Result Hash 1-7 Bits Incoming Packets Mask Function (32 Bits) 32-Bit Hash Result Hash Type Figure 29: RSS Receive Processing Sequence The BCM5755 and BCM5755M devices implement the above RSS algorithm in hardware except for the step of adding the Base CPU Number to the value from Indirection Table.
Page 132 BCM5722 Programmer’s Guide 10/15/07 Secret Hash Key The hash key that will be used for RSS hash. For the Toeplitz hash, the hash key size is 40 bytes for IPv6 and 16 bytes for IPv4. The host software should program the hash key in hash key registers at offset 0x670 to 0x697.
Page 133 Associated with each ring are two indices that control its operation. These indices are the producer index and the consumer index, which are not shared between the host software and the BCM5722 Ethernet controller. In the case of send rings, the host software controls the producer index by adding elements (initializing a Send BD) to the ring.
Page 134: Figure 30: Relationships Between All Components Of A Send Ring
“Send Rings” on page 74 for a full discussion of the send RCB). All the fields are in big-endian ordering as required by the BCM5722 Ethernet controller. The RCBs of the send rings are located in the device Miscellaneous Memory Region at offset 0x0100.
Page 135: Figure 32: Relationship Between Send Buffer Descriptors
NIC’s internal memory where they are waiting to be consumed. The staging area can hold up to 128 entries per-ring, and BCM5722 Ethernet controller tries to keep the staging area full at all times by constantly monitoring the consumer and producer index (the algorithm for accomplishing this is beyond the scope of this manual).
Page 136 IP datagram and TCP segments containing options. For the BCM5722 Ethernet controller to compute the checksum and insert it into the outgoing frame, the host software must set the appropriate control bits in the send buffer descriptors associated with the frame and seed the checksum field with zero or with the pseudo header checksum.
Page 137: Figure 33: Scatter Gather Of Frame Fragments
Most often, the host software requests the NIC to transmit a frame that spans several physical fragments that are arbitrary in size and buffer alignment. This requires the BCM5722 Ethernet controller to gather all these fragments during a DMA process into a continuous data stream for transmission.
Page 138 802.1Q VLAN tag inserted. The BCM5722 Ethernet controller allows the host software to enable or disable tag insertion on a per-packet basis. To send a frame with a VLAN tag, the host software must initialize the first send buffer descriptor of a packet with the VLAN tag value and set the VLAN_TAG bit of Send BD Flags field (see “Send Rings”...
Page 139: Figure 34: Transmit Data Flow
Programmer’s Guide BCM5722 10/15/07 The following figure shows the basic driver flow to send a packet. Host Memor Host Memory Send BD 1 Frame Send BD 2 Buffer 1 Send BD 3 Send BD 4 Status Buffer 2 Send BD 5...
Page 140: Figure 35: Basic Driver Flow To Send A Packet
BCM5722 Programmer’s Guide 10/15/07 OS asks NIC Driver to send a packet Is the NIC enabled to send packets? Return appropriate error code to OS. Examine packet (if necessary) and decide which send ring to use. Does the NIC have enough free Queue packet for later transmission.
Page 141 Programmer’s Guide BCM5722 10/15/07 S ec t io n 8: Dev ic e Co nt rol NITIALIZATION ESCRIPTION This section provides programmers a procedure for initializing the NetXtreme family of devices. There is a specific sequence of steps that must be taken to enable this device. This section assumes the host programmer can allocate physical memory for various control blocks using OS/RTOS specific methods.
Page 142 BCM5722 Programmer’s Guide 10/15/07 11. Enable the MAC memory arbiter. Set the Enable bit in the Memory Arbiter Mode register (see “Memory Arbiter Mode Register (Offset 0x4000)” on page 301). 12. Initialize the Miscellaneous Host Control register (see “Miscellaneous Host Control Register (Offset 0x68)” on page 204): a.
Page 143 Mbuf Pool Base Address and Mbuf Pool Length registers. So, Broadcom recommends to not to change these Mbuf Pool registers from driver software unless the it is required to load a special firmware from driver. For any reason, if it is required to modify either of the Mbuf...
Page 144: Table 35: Recommended Bcm5722 Ethernet Controller Memory Pool Watermark Settings
BCM5722 Programmer’s Guide 10/15/07 28. Configure MAC memory pool watermarks. Broadcom has run hardware simulations on the Mbuf usage and strongly recommends the settings shown in Table 35. These settings/values will establish proper operation for 10/100/1000 speeds. Host software must configure the MAC RX Mbuf Low Watermark and Mbuf High Watermark registers (“MAC RX...
Page 145: Table 37: Recommended Bcm5722 Ethernet Controller Standard Ring Initialization Settings For Internal Memory Only
Programmer’s Guide BCM5722 10/15/07 Table 37: Recommended BCM5722 Ethernet controller Standard Ring Initialization Settings for Internal Memory Only RCB Data Field Recommended Value Notes NIC Ring Address(32-bits) 0x6000 Max_Length 0x200 Number of Elements in the ring. The valid configuration values are 32, 64, 128, 256, and 512.
Page 146 0x3C0C)” on page 295) specify the number of clock ticks elapsed before an interrupt is driven. The clock begins ticking after RX/TX activity. Broadcom recommends the settings shown in Table 38 on page Bro adco m C orp or atio n...
Page 147: Table 38: Recommended Bcm5722 Ethernet Controller Host Coalescing Tick Counter Settings
“Receive Max Coalesced BD Count (Offset 0x3C10)” on page 296 “Send Max Coalesced BD Count (Offset 0x3C14)” on page 296) specify the number of frames processed before an interrupt is driven. Broadcom recommends the settings shown in Table Table 39: Recommended BCM5722 Ethernet Controller Host Coalescing Frame Counter Settings...
Page 148 286). 71. Enable the send data initiator functional block. Set the Enable bit in the Send Data Initiator Mode register (see “Send Data Initiator Mode Register (Offset 0x0C00)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787, and BCM5906 Only” on page 269).
Page 149 Optional—the PMCSR register is reset to 0x00 after chip reset. Software may optionally reconfigure this register if the device is being moved from D3 hot/cold. 80. Program Hardware to control LEDs. Write 0x00 to LED Controls register. LEDs on the BCM5722 Ethernet controller reference designs are tied to the physical layer.
Page 150 HUTDOWN To power down the BCM5722 Ethernet controller, its state machines must be disabled in specific sequence as shown below. The host software must clear the Enable bit of each state machine and poll the bit until it is cleared. The maximum poll period that software must wait for the enable bits to clear is 2 ms;...
Page 151 MAGE The RISC cores in the BCM5722 Ethernet controller chips execute the MIPS-2 instruction set. Broadcom uses a GNU tool kit to create the firmware binary code. The output from the GNU build is a C language header file, which contains the machine code for the embedded RISC cores.
Page 152: Figure 36: Firmware Image Moved To Scratch Pad/Rxmbuf
RISC Core relative addresses; the host must translate each address to a BCM5722 Ethernet controller’s register space region. In summary, the address offsets in the header file are relative to the local memory address ranges specified in Table 41 for the RX and TX RISC respectively.
Page 153 Programmer’s Guide BCM5722 10/15/07 RISC P ESET ROCESSOR The RX processor can be reset by setting the Reset RX RISC Bit of the RX RISC Mode register (see “RX RISC Mode Register (Offset 0x5000)” on page 317). This bit is self-clearing bit; it will be cleared once internal reset of processor is completed.
Page 154 BCM5722 Programmer’s Guide 10/15/07 IRMWARE OWNLOAD ROCEDURE The host driver should use register indirect access to modify both the scratch pad and RISC register space. See “Pseudocode” on page 132 Section 9: “PCI”. 1. Halt the RX RSIC Core (see “Halt RISC Procedure”...
Page 155: Table 42: Mac Address Registers
However, most host software will initialize the registers of the four MAC addresses to the same MAC address since a NIC usually has only one MAC address. When flow control is enabled on the BCM5722 Ethernet controller, the MAC Address 0 is used as the source address for sending PAUSE frames (see “Pause Control Frame”...
Page 156 ALCULATION The BCM5722 Ethernet controller uses the standard 32-bit CRC required by the Ethernet specification as its FCS in all packets. The checksum is the 32-bit remainder of the polynomial division of the data taken as a bit stream of polynomial coefficients and a predefined constant, which also represents binary polynomial coefficients.
Page 157: Table 43: Multicast Hash Table Registers
MAC H NITIALIZING THE EGISTERS The 128-bit multicast hash table is treated as a single object occupying four BCM5722 Ethernet controller registers starting at offset 0x0470 (see Table 43). The 128-bit value follows the big-endian ordering required by BCM5722 Ethernet controller.
Page 158 In promiscuous mode of operation, the BCM5722 Ethernet controller accepts all incoming frames that are not filtered by the active receive rules regardless of the destination MAC address. In other words, the BCM5722 Ethernet controller operating in promiscuous mode ignores multicast and MAC address filtering (“Multicast Hash Table...
Page 159 ETUP ONFIGURATION The host software may configure the BCM5722 Ethernet controller to discard the received broadcast frames by using two receive rules as defined below. The BCM5722 Ethernet controller parses all incoming frames according to these receive rules and discards those frames that have a broadcast destination address (see “Receive Rules Setup and Frame...
Page 160: Table 44: Bcm5755/Bcm5755M Address Map
APS AND ONFIGURATION The BCM5722 Ethernet controller provides internal SRAM memory for Ring buffers, Tx Packet Mbuf memory, Rx Packet Mbuf Memory, Misc shared memory, and Status block. The memory maps show how the internal SRAM is mapped into the...
Page 161 Programmer’s Guide BCM5722 10/15/07 Table 44: BCM5755/BCM5755M Address Map (Cont.) Region Size NIC CPU View Host Flat View Host Standard View Host UNDI View Send Ring 1 KB 0x00004000– 0x01004000– 0x00004000–* 0x00004000–* 0x000043FF 0x010043FF 0x000043FF 0x000043FF Unmapped 7 KB 0x00004400–...
Page 162: Table 45: Bcm5787/Bcm5787M/Bcm5754/Bcm5754M Address Map
BCM5722 Programmer’s Guide 10/15/07 Table 45: BCM5787/BCM5787M/BCM5754/BCM5754M Address Map Region Size NIC CPU View Host Flat View Host Standard View Host UNDI View Unmapped 256B 0x00000000– 0x01000000– 0x00000000–* 0x00000000–* 0x000000FF 0x010000FF 0x000000FF 0x000000FF Send Ring RCB 0x00000100– 0x01000100– 0x00000100–* 0x00000100–*...
Page 163 Programmer’s Guide BCM5722 10/15/07 Table 45: BCM5787/BCM5787M/BCM5754/BCM5754M Address Map (Cont.) Region Size NIC CPU View Host Flat View Host Standard View Host UNDI View High Priority 512B – 0x00000200–0x00000 0x00000200–0x00000 0x00005800–** Mailbox 0x000059FF Functional 31 KB 0xC0000400–0xC0 0x00000400–0x00007 0x00000400–0x00007 0x00000100–**...
Page 164: Table 46: Bcm5906/Bcm5906M Address Map
BCM5722 Programmer’s Guide 10/15/07 Table 46: BCM5906/BCM5906M Address Map Region Size NIC CPU View Host Flat View Host Standard View Host UNDI View Unmapped 256B 0x00000000– 0x01000000– 0x00000000–* 0x00000000–* 0x000000FF 0x010000FF 0x000000FF 0x000000FF Send Ring RCB 0x00000100– 0x01000100– 0x00000100–* 0x00000100–*...
Page 165 Programmer’s Guide BCM5722 10/15/07 * Indirect access via Memory Window Base Address and Memory Window Data register pair ** Indirect access via Register Window Base Address and Register Window Data register pair Note: Reads to unmapped space return all zero. Writes to unmapped space are dropped internally.
Page 166 BAR. The BCM5722 Ethernet controller implements two modes of memory mapped I/O—Standard and Flat. I/O mapped I/O is not supported by the BCM5722 Ethernet controller, and there are no I/O space registers.
Page 167: Figure 37: Local Contexts
The second is a memory block. The register and memory blocks map into address spaces based on processor context. For example, the BCM5722 Ethernet controller has an on-chip RISC processor. This RISC processor will have an internal view of the register and memory blocks. This view is one large contiguous and addressable range, where the register block maps starting at offset 0xC0000000.
Page 168: Figure 38: Header Type Register 0Xe
UNCTIONAL VERVIEW PCI Configuration Space Registers The BCM5722 Ethernet controller configuration space can be broken into two regions: Header and Device Specific. Table 92 on page 186 shows the registers implemented to support PCI/PCI-X/PCIe functionality in the BCM5722 Ethernet controller.
Page 169: Figure 39: Header Region Registers
Capabilities 0x40 0xFF Capabilities 0x64 Figure 39: Header Region Registers See the PCI configuration registers in Section 12: “BCM5722 Ethernet Controller Register Definitions” on page 186. Bro adco m Co rp or atio n Document 5722-PG101-R Configuration Space Page 110...
Page 170 Device-specific registers are not defined in the PCI 2.2 specification and are exactly as the name implies—specific to the BCM5722 Ethernet controller. These registers may be used by host software to configure or change the operational state of the MAC. The most notable feature exposed via the Device Specific registers is Indirect Mode. Host or system software may use Indirect Mode to access BCM5722 Ethernet controller local memory and register space;...
Page 171: Figure 40: Device-Specific Registers
Programmer’s Guide BCM5722 10/15/07 Bytes 0x68 Miscellaneous Host Control 0x6C DMA Read/Write Control 0x70 PCI State 0x74 Clock Control 0x78 Register Base Address 0x7C Memory Window Base Address 0x80 Register Data R/W Configuration 0x84 Registers Memory Window Data R/W 0x88...
Page 172: Table 47: Device Specific Registers
204) to enable indirect mode. Indirect Register Access Two PCI configuration space register pairs give host software access to the BCM5722 Ethernet controller register block. The Register_Base_Address register creates a position in the MAC register block. Valid positions range from 0x0000–0x8000 and 0x30000–0x38800 ranges.
Page 173: Figure 41: Register Indirect Access
Programmer’s Guide BCM5722 10/15/07 Register Indirect Access BCM57XX Ethernet Controller Register Block PCI Configuration Space 0x00000000 0x00000400 Address may be located anywhere BCM57XX Ethernet Controller Registers Address may be located anywhere 0x00008000 BusX DeviceY Function Z Not Accessible via Register...
Page 174 Memory indirect mode operates in the same fashion to register indirect mode. There is a PCI configuration space register pair, which is used to access the BCM5722 Ethernet controller memory block. The Memory_Window_Base_Address register positions a pointer/cursor in the local memory block. Unlike the Register_Base_Address register, the Memory_Window_Base_Address register may position at any valid offset.
Page 175: Figure 42: Indirect Memory Access
Programmer’s Guide BCM5722 10/15/07 Indirect Memory Access BCM57XX Ethernet Controller PCI Configuration Space Memory Block 0x00000000 Address may be located anywhere Internal Memory BusX DeviceY Function Z Memory Base Address Address may be located anywhere 0x00020000 Memory Data Register Figure 42: Indirect Memory Access...
Page 176 The UNDI mailboxes are shadows of BCM5722 Ethernet controller mailbox registers. All mailboxes reside in the BCM5722 Ethernet controller register block, not memory block. Unlike register and memory indirect access, the UNDI Mailboxes shadows are mapped 1:1 to a BCM5722 Ethernet controller register; these shadow registers do not have an address register.
Page 177: Figure 43: Low-Priority Mailbox Access For Indirect Mode
Programmer’s Guide BCM5722 10/15/07 Indirect Mailbox Access PCI Configuration Space BCM57XX Register Block 0x00000000 0x00000400 BusX DeviceY Low Priority Function Z Not Aliased Mailbox Region UNDI Rx BD Std Ring 0x00005800 Producer Index Mailbox 0x00005868 Rx BD Std Ring Producer Index...
Page 178: Figure 44: Standard Memory Mapped I/O Mode
Programmer’s Guide 10/15/07 Standard Mode Standard mode is the most useful memory mapped I/O view provided by the BCM5722 Ethernet controller (see Figure 44). 64K of host memory space must be made available. The PnP BIOS or OS will program BAR0 and BAR1 with a base address where the 64K address region may be decoded.
Page 179: Figure 45: Memory Window Base Address Register
Memory_Window_Base_Address + OFFSET. Host software must not read/write from any address greater than PCI_BAR + 64K, since this memory space is not decoded by the BCM5722 Ethernet controller. Such an access may be decoded by another device, or simply go unclaimed on the PCI bus.
Page 180: Figure 46: Standard Mode Memory Window
BCM5722 Programmer’s Guide 10/15/07 Standard Mode Memory Window PCI Configuration Space Host Memory Address Space Local Memory Address Space 0x00000000 0x00000000 Physical BusX Memory DeviceY Function Z Window may be located anywhere Mem Wnd Base Addr Internal Host software may...
Page 181 Ethernet controller resources host memory mapped; diagnostic software is an example application. Mailboxes, Send Rings, Receive Rings, and Local Memory are directly mapped into the host memory space. Unlike standard mode, the BCM5722 Ethernet controller’s local memory is addressable through host memory mapped I/O. Flat mode should not be used when there are limitations on the amount of memory mapped I/O available.
Page 182: Figure 47: Flat Mode Memory Map
BCM5722 Programmer’s Guide 10/15/07 PCI Configuration Space Host Memory Address Space Physical BusX Memory DeviceY Function Z 0x00000000 PCI Cfg Space Registers BAR0 (Shadow Copy) BAR1 Reserved 0x00000200 High Priority Mailboxes 0x00000400 Registers 0x00008000 Memory Window Reserved 0x00100000 IRQ Mailbox 0-3...
Page 183: Table 49: Pci Address Map Flat View
PCI Configuration space 256 bytes 0x00000100–0x000001FF PCIe Extended Configuration space 256 bytes 0x00000200–0x000003FF High Priority Mailboxes 512 bytes 0x00000400–0x00007FFF BCM5722 Ethernet controller registers 31 KB 0x00008000–0x0000FFFF Memory Window 32 KB 0x00100000–0x00100007 Interrupt Mailbox 0 8 bytes 0x00104000–0x00104007 Interrupt Mailbox 1 8 bytes 0x00108000–0x00108007...
Page 184 Memory 16 MB The proceeding host memory ranges are relative to the BCM5722 Ethernet controller PCI BAR—the address decodes are BAR + offset. Offsets 0x00–0xFF contain a shadow copy of the PCI configuration space registers. Host software may use this memory map to read/write to PCI configuration space registers. Address offsets 0x200–0x3FF are high priority mailboxes.
Page 185 Second, host software may access the memory-mapped range 0x01000000 to 0x01FFFFFF. The second technique is preferable since flat mode has made 32 MB of host memory-mapped space available. Software does not need to use the memory window since the BCM5722 Ethernet controller’s entire memory region is memory- mapped.
Page 186: Figure 48: Flat Mode Memory Map
BCM5722 Programmer’s Guide 10/15/07 Address Range Name 0x00100000 - 0x00100007 IRQ MB0 Host Memory Address 0x00104000 - 0x00104007 IRQ MB1 Space 0x00108000 - 0x00108007 IRQ MB2 0x0010C000 - 0x0010C007 IRQ MB3 Address Range Name 0x00000000 PCI Cfg Space Registers 0x00110000 - 0x00110007...
Page 187: Figure 49: Techniques For Accessing Bcm5722 Ethernet Controller Local Memory
0x001C0000 Tx BD Ring 1-16 NIC Producer Index Reserved 0x01000000 Device External Memory Memory 0x01FFFFFF 0x00020000 Figure 49: Techniques for Accessing BCM5722 Ethernet Controller Local Memory Bro adco m Co rp or atio n Document 5722-PG101-R Configuration Space Page 128...
Page 188: Figure 50: Pci Command Register
The PCI_State register is 32-bits wide. Operating mode is set with the Flat_View bit in the PCI_State register. When the Flat_View bit is asserted, the BCM5722 Ethernet controller decodes a 32M of block host memory. When the Flat_View bit is de-asserted, the BCM5722 Ethernet controller decodes a 64K block of host memory.
Page 189: Figure 51: Pci Base Address Register
Figure 51: PCI Base Address Register The BCM5722 Ethernet controller 64K memory mapped I/O block is determined by the first programmable bit in the BAR. When the MAC is configured in standard mode, the mask 0xFFFF0000 identifies the BAR bits, which are programmable. Bit 16 is the first bit encountered in the scan upward, which is programmable;...
Page 190: Figure 53: Pci Base Address Register Bits Read In Flat Mode
10/15/07 When the BCM5722 Ethernet controller is programmed in flat mode, a 32M region of memory mapped I/O needs to be made available. The PnP BIOS/OS will probe the BAR, and scan upwards looking for the first programmable bit. Again, bits 0–3 are ignored.
Page 191 Programmer’s Guide BCM5722 10/15/07 SEUDOCODE Variable BCM57XXMemAddr represents a local memory address. • • Variable BCM57XXMemBase represents a 32K aligned local memory address. Variable BCM57XXMemOffset represents a byte offset. • • PCI_CFG_WRITE (address, value ) is a routine to write the device's PCI configuration space register.
Page 192: Figure 54: Read And Write Channels Of Dma Engine
The read/write DMA engines both drive the PCIe interface. Normally, each DMA engine alternates bursts to the PCIe bus, and both interfaces may have outstanding transactions on the PCI bus. The BCM5722 architecture identifies two channels—a read DMA channel and a write DMA channel. Each channel corresponds to the appropriate DMA engine (see Figure 54).
Page 193 Read/Write DMA Engines Software must enable the bus master DMA bit for the BCM5722 Ethernet controller. The BCM5722 Ethernet controller is a bus-mastering device and the PCI interface requires that the Bus_Master enable bit be set by either the BIOS or host device driver.
Page 194: Table 51: Pci -X Registers
Split_Completion_Message_Class Split_Completion_Message_Index XPANSION ESCRIPTION The expansion ROM on the BCM5722 Ethernet controller is intended for implementation of PXE (Preboot Execution Environment). The devices support expansion ROM of up to 16 MB. PERATIONAL HARACTERISTICS By default, the Expansion ROM is disabled and the firmware has to explicitly enable this feature by setting PCI_State.PCI_Expansion_ROM_Desired bit to one (see...
Page 195 PXE normally resides in the system BIOS. In the NIC implementation, PXE image is stored in the NVRAM. Upon power on reset of the BCM5722 Ethernet controller, the RX RISC will load the bootcode from the NVRAM into RX RISC scratch pad and execute.
Page 196: Figure 55: Power State Transition Diagram
HARACTERISTICS Figure 55 applies to the BCM5722 Ethernet controller reference designs. The MAC GPIO pins are available for application specific usage; however, Broadcom encourages both software and hardware engineers to follow the Broadcom design guidelines and application notes. NIC and LOM designs use external board level logic to switch power regulators for D3 ACPI mode.
Page 197 82) to move the MAC into a D0 active state. When the BCM5722 NetXtreme devices detect that main power is lost and it's still in the D0 state, it will reset itself to the D3 (Cold) state and then operate in 10/100 mode, like the OOB WOL state.
Page 198: Table 52: Gpio Usage For Bcm5700/Bcm5701 Power Management For Broadcom Drivers
TATE Table 54 shows the power supply to various power pins on the BCM5722 Ethernet controller. This table assumes that host software has switched power regulators using GPIO pins 0, 1, and 2. Table 54: BCM5722 Ethernet controller Power Pins...
Page 199 NIC/LOM. For example, the BCM5722 Ethernet controller can assert PME from both D3 hot and cold states. The PME_Support bit field in the PMC register will reflect this capability.
Page 200: Table 55: Power Management Registers
BCM5722 Programmer’s Guide 10/15/07 EGISTER UICK ROSS EFERENCE The BCM5722 Ethernet controller power management registers are listed in Table Table 55: Power Management Registers Register Description Cross Reference Misc Local Control Misc_Pin_0_Output GPIO pin 0 “Miscellaneous Local Control Register (Offset 0x6808)” on...
Page 201: Table 56: Endian Example
Programmer’s Guide BCM5722 10/15/07 NDIAN ONTROL YTE AND WAPPING ACKGROUND There are two basic formats for storing data in memory—little-endian and big-endian. The endianess of a system is determined by how multibyte quantities are stored in memory. A big-endian architecture stores the most significant byte at the lowest address offset while little-endian architecture stores the least significant byte at the lowest address offset.
Page 202 However, many hosts (e.g., x86 systems) use the little-endian format, and the PCI bus uses the little-endian format. Therefore the BCM5722 Ethernet controller has a number of byte swapping options that may be configured by software so that Little or Big Endian hosts can interface as seamlessly as possible with BCM5722 Ethernet controller over PCI. The BCM5722 Ethernet controller has the following bits that control byte and word swapping: •...
Page 203: Figure 56: Default Translation (No Swapping) On 64-Bit Pci
PCI accesses. Thus, these bits affect the byte order when the host is directly reading/writing to registers or control structures that are physically located on the BCM5722 Ethernet controller. These bits do not affect the byte ordering of packet data or other structures that are mastered (DMAed) by the BCM5722 Ethernet controller.
Page 204: Figure 58: Word Swap Enable Translation On 32-Bit Pci (No Byte Swap)
144. Therefore, if a software driver running on an x86 host (Little Endian) referenced on-chip data structures as they are defined in the BCM5722 Ethernet controller data sheet, the driver should set the Enable Endian Word Swap bit. By setting this bit, the translation would be as follows:...
Page 205: Table 60: Big-Endian Internal Packet Data Format
However, when the data gets transferred across PCI, there could be confusion about the correct byte ordering because PCI is Little Endian whereas BCM5722 Ethernet controller is a Big Endian device. So, in order to provide flexibility for different host processor/memory architectures, BCM5722 Ethernet controller can order this data on PCI in four different ways depending on the settings of the Word Swap Data, and Byte Swap Data bits.
Page 206: Table 61: 64-Bit Pci Bus (Wsd = 0, Bsd = 0)
BCM5722 Programmer’s Guide 10/15/07 Word Swap Data = 0, and Byte Swap Data = 0 Table 61: 64-Bit PCI Bus (WSD = 0, BSD = 0) 63–56 55–48 47–40 39–32 31–24 23–16 15–8 7–0 Table 62: 32-Bit PCI Bus (WSD = 0, BSD = 0) 31–24...
Page 207: Table 65: 64-Bit Pci Bus (Wsd = 1, Bsd = 0)
Programmer’s Guide BCM5722 10/15/07 Word Swap Data = 1, and Byte Swap Data = 0 Table 65: 64-Bit PCI Bus (WSD = 1, BSD = 0) 63–56 55–48 47–40 39–32 31–24 23–16 15–8 7–0 Table 66: 32-Bit PCI Bus (WSD = 1, BSD = 0) 31–24...
Page 208: Table 69: Send Buffer Descriptor (Big-Endian 64-Bit Format)
The Word Swap Non-Frame Data, and Byte Swap Non-Frame Data bits affect the byte ordering of certain shared memory data structures (buffer descriptors, statistics block, etc.) when those structures are transferred across PCI. The following table shows as example of how a Send Buffer Descriptor is stored internally in the BCM5722 Ethernet controller.
Page 209: Table 71: Send Buffer Descriptor (Little-Endian 32-Bit Format) With No Swapping
Programmer’s Guide BCM5722 10/15/07 Word Swap Non-Frame Data = 0 and Byte Swap Non-Frame Data = 0 This would require the software to use the following little-endian data structure on the host: Table 71: Send Buffer Descriptor (Little-Endian 32-Bit format) with No Swapping...
Page 210: Table 74: Send Buffer Descriptor (Big-Endian 32-Bit Format) With Word And Byte Swapping
BCM5722 Programmer’s Guide 10/15/07 Word Swap Non-Frame Data = 1 and Byte Swap Non-Frame Data = 1 This requires the software to use the following big-endian data structure on the host: Table 74: Send Buffer Descriptor (Big-Endian 32-bit format) with Word and Byte Swapping...
Page 211 ETECTS The BCM5722 Ethernet controller has two different methods that it can use to determine if the Ethernet link is up or down. The link will be down if the Ethernet cable is not properly attached at both ends of the network. Link will be up only if the cable is properly attached and the devices at both ends of the cable recognize that link has been established.
Page 212 “Transceiver Registers” on page 414. The integrated PHY registers are accessed via a process called MDIO. The integrated PHY is connected to the BCM5722 Ethernet controller through an internal MDIO bus (MDIO and MDC pins). Software accesses PHY’s registers via MDIO through the BCM5722’s MI_Communication register (see...
Page 213 Programmer’s Guide BCM5722 10/15/07 // If auto-polling is enabled, turn it back on If (AutoPolling_Enabled == TRUE) then Begin Mi_Mode.PortPolling = 1 // Now return the value that we read (lower 16 bits of reg) Return (Value32 & 0xffff) Writing a PHY Register...
Page 214 BCM5722 Programmer’s Guide 10/15/07 MDI R EGISTER CCESS Configuring physical devices and querying the status of physical devices are done via the MDIO interface (MDC and MDIO). Note: This procedure is PHY-independent. The MAC access to the PHY is the same for the entire NetXtreme family.
Page 215 Auto-Access Method The BCM5722 Ethernet controller has a built-in interface to access physical device registers without having to control MDC and MDIO pins by software/firmware. It provides an easy way to access the physical device register. To use this mode, MDI_Control_Register.MDI_Select has to be cleared to 0. The MI_Communication_Register (see “MI...
Page 216 BCM5722 Programmer’s Guide 10/15/07 To write a value of 0x1000 into 16-bit PHY register at offset 0x0 of a PHY device which is strapped to PHY address 1, perform the following steps: 1. MI_Communication_Register.Register_Address is set to 0x0. 2. MI_Communication_Register.PHY_Addr is set to 1.
Page 217 Appendix B ”PC Power Management” on page 518 for more details on power management). While the BCM5722 Ethernet controller is in a D3 state, the RX MAC will filter incoming packets. The RX MAC compares incoming traffic for Interesting Packet pattern matches. The BCM5722 Ether- net controller asserts the PCI PME signal, when a positive WOL packet comparison is made.
Page 218: Figure 61: Wol Functional Block Diagram
VERVIEW The BCM5722 Ethernet controller is capable of WOL in 10/100 Mbps for copper-based controllers. Note: When configured for WOL in 1000-Mbps mode, the BCM5722 Ethernet controller draws more than the 375 mA allowed by the PCI specification. The BCM5722 Ethernet controller uses the TX FIFO to store pattern data (see Figure 61).
Page 219: Table 75: Required Memory Regions For Wol Pattern
WOL pattern before each D0 to D3 transition. The RX/TX MAC places packets into this internal memory and the WOL pattern is overwritten during normal operation. When the BCM5722 Ethernet control- ler operates in D0 state, internal data structures use the same memory location as the WOL pattern. Host software should re-initialize the WOL pattern before each WOL sleep transition.
Page 220 A stream is a comparison operation on RX frame(s). When the MAC is running at 10/100 Mbps wire speed, nine different patterns can be compared against the RX frame(s). The BCM5722 Ethernet controller moves RX frame(s) into nine parallel comparators, and the frame is matched simultaneously. The MAC is capable of filtering nine different patterns in 10/100 modes.
Page 221: Figure 62: Comparing Ethernet Frames Against Available Patterns (10/100 Ethernet Wol)
Programmer’s Guide BCM5722 10/15/07 10/100 Ethernet WOL Frame 0 Skip C0, C1,C2,C3 Frame 1 Skip B0, B1, B2, B3, B4, B5 Frame 2 Skip A0,A1,A2,A3,A4,A5 Control Stream Stream Stream ACPI Offset Field A0, A1 B0, B1 C0, C1 Patterns A2,A3...
Page 222: Figure 63: Unused Rows And Rules Must Be Initialized With Zeros
Pattern Data Structure The maximum number of entries in either 10/100 or 1000 mode is 128. The BCM5722 Ethernet controller cannot process a pattern that requires more than 128 entries. The size of an entry will vary based on 10/100 or 1000 Mbps mode. Additionally, all unused rows must be initialized with zeros.
Page 223: Table 77: Frame Control Field For 10/100 Mbps Mode
Programmer’s Guide BCM5722 10/15/07 Table 77: Frame Control Field for 10/100 Mbps Mode Bits Field Description Access 63:62 Reserved S0 High Byte Enable Enable S0 higher byte for comparison S0 Low Byte Enable Enable S0 lower byte for comparison S1 High Byte Enable...
Page 224: Table 79: Firmware Mailbox Initialization
WOL mode since the PHY should not be reset. Before the host software issues a reset to the BCM5722 Ethernet controller, it must write the T3_MAGIC_NUM to the shared memory address T3_FIRMWARE_MAILBOX (0xb50). This address is a software mailbox, which bootcode polls before it resets the PHY.
Page 225: Table 81: Wol Mode Clock Inputs
Programmer’s Guide BCM5722 10/15/07 Power Management The clocking inputs need to be modified for WOL mode (see Table 81). The RX CPU is not required during WOL operation, so its clock can be disabled. The MAC has an internal phase-locked loop that clocks internal logic at 133 MHz. Software must select an alternate clocking source and then disable this PLL.
Page 226: Table 83: Phy Wol Mode Control Registers
BCM5722 Programmer’s Guide 10/15/07 EGISTER UICK ROSS EFERENCE Integrated PHYs Table 83 lists the WOL mode control registers in the integrated PHYs. Table 83: PHY WOL Mode Control Registers MDI Register Bit(s) Name Description Cross Reference Auto_Negotation 10_BASE_TX_Half_ Advertise to link partner that local PHY is “Auto-Negotiation Advertisement...
Page 227: Table 84: Integrated Mac Wol Mode Control Registers
Programmer’s Guide BCM5722 10/15/07 Integrated MACs Table 84 lists the WOL mode control registers in the BCM5722 Ethernet controllers. Table 84: Integrated MAC WOL Mode Control Registers Register Bit(s) Name Description Cross Reference WOL_Pattern_ This register points to an internal “WOL Pattern Pointer Register...
Page 228 Power Control)” on page 447. 8. For Interesting Packet WOL Only: Set up the Interesting Packet pattern in BCM5722 Ethernet controller local memory. 9. For Interesting Packet WOL Only: Write a pointer value to the “WOL Pattern Pointer Register (Offset 0x430)” on page 249.
Page 229 17. In NIC applications, switch from VMAIN to VAUX in order to prevent a GRC reset. Set the required GPIOs of BCM5722 Ethernet controller if any of them are used for switching the power from VMAIN to VAUX.
Page 230: Transmit Mac
After the RX MAC receives this number of frames, it will drop subsequent incoming frames until the MBUF High Water Mark is reached. The IEEE 802.3 pause control frame contains a pause_time field. The BCM5722 Ethernet controller inserts a time quanta into the pause_time field. Software should set the Enable_Long_Pause bit in the Transmit_MAC_Mode register to configure long pause quanta.
Page 231: Statistics Block
The relationships of flow control statistics are discussed in this section. Xon/Xoff statistical counters are related to internal BCM5722 Ethernet controller flow control states. Xon is associated to transmit enabled state and Xoff is associated to transmit disabled state. These Xon/Xoff states are not part of the IEEE 802.3 specification;...
Page 232: Phy Auto-Negotiation
Auto_Negotation_Link_Partner_Ability_Register does not set the Pause_Capable bit. The BCM5722 Ethernet controller should not send pause frames to this link partner since flow control is not implemented or disabled. The BCM5722 Ethernet controller can still accept pause frames, but sending a pause frame does not yield a preferred result.
Page 233: Integrated Macs
Programmer’s Guide BCM5722 10/15/07 Integrated MACs Table 90 lists the flow control registers in the BCM5722 Ethernet controllers. Table 90: Integrated MAC Flow Control Registers Register Bit(s) Name Description Cross Reference Receive MAC Mode Enable_Flow_Control Enable automatic processing of IEEE “Receive MAC Mode...
Page 234 BCM5722 Programmer’s Guide 10/15/07 Driver_Flow_Capability = FLOW_CONTROL_RECEIVE_PAUSE Else Driver_Flow_Capability = NONE //The local physical layer was not configured to advertise Asymmetric pause Else (Auto_Neg_Link_Partner_Ability_Reg.Pause_Capable == ENABLED) Then Driver_Flow_Capability = FLOW_CONTROL_TRANSMIT_PAUSE \ | FLOW_CONTROL_RECEIVE_PAUSE Else Driver_Flow_Capability = NONE // The local physical layer was not configured to advertise Pause capability Else If (Auto_Neg_Advertise_Reg.Asymetric_Pause == ENABLED) Then...
Page 235 Programmer’s Guide BCM5722 10/15/07 if ( Driver_Flow_Capability & FLOW_CONTROL_TRANSMIT_PAUSE ) Then Transmit_MAC_Mode_Control_Register.Enable_Flow_Control = ENABLED // Link is up on the local PHY Bro adco m Co rp or atio n Document 5722-PG101-R Flow Control Page 176...
Page 236: Section 11: Interrupt Processing
HARACTERISTICS The BCM5722 Ethernet controller DMAs the status block to host memory before a line interrupt or MSI is generated. The host ISR reads the update bit at the top of the status block and checks whether this bit is set to 1 or not. When set to 1, the updated bit of status block indicates the host that the status block has been refreshed by the MAC.
Page 237: Registers
Programmer’s Guide BCM5722 10/15/07 EGISTERS The BCM5722 Ethernet controller supports a variety of registers that affect status block updates and interrupt generation (see Table 91). Table 91: Interrupt-Related Registers Register Cross Reference Miscellaneous Host Control register. “Miscellaneous Host Control Register (Offset 0x68)” on page 204.
Page 238: Msi
ISR to force all posted memory writes to be flushed to the host memory. RADITIONAL NTERRUPT CHEME A simplified block diagram showing traditional interrupt scheme is depicted in Figure BCM5722 Ethernet Interrupt A Controller BCM5700 PCI Bus PCI Host...
Page 239: Message Signaled Interrupt
PCI host bridge yet. The scheme to resolve this problem is to do a dummy read of the BCM5722 Ethernet controller in the beginning of the interrupt service routine.
Page 240: Pci Configuration Registers
MSI Data This is a 16-bit field. The least significant three bits can be modified by the BCM5722 Ethernet controller when it writes MSI message to host. The DWORD data for the MSI message is depicted as shown in...
Page 241: Host Coalescing Engine
Host_Coalesing_Mode register. The default of these bits is zeros. IRMWARE The BCM5722 Ethernet controller provides a way for firmware executed by RX RISC to generate MSI messages. Firmware can generate MSI messages by using MSI_FIFO_Access register (Offset 0x6008). For example, if firmware wants to generate an MSI message with least significant 3-bit as 0x2, it will write 2 to MSI_FIFO_Access register.
Page 242: Basic Driver Interrupt Processing Flow
BCM5722 Programmer’s Guide 10/15/07 ASIC RIVER NTERRUPT ROCESSING LOWCHART FOR ERVICING AN NTERRUPT The following figure shows the basic driver interrupt service routine flow. NIC encounters an Interrupt event and asserts in IN TA# line to interrupt host H ost OS receives Interrupt and calls NIC driver's ISR Driver reads the "status w ord"...
Page 243: Interrupt Procedure
2. Read and save the value of the Status Tag field of the Status Block (see “Status Block” on page 53). 3. Claim interrupt. Determine if the BCM5722 Ethernet controller action is required. Read the Updated bit of the status word (see Table 27 on page 57).
Page 244: Other Configuration Controls
BCM5722 Programmer’s Guide 10/15/07 THER ONFIGURATION ONTROLS ROADCOM Enabled by setting the Mask_Interrupt_Mode bit (bit 8) of the Miscellaneous Host Control register (see “Miscellaneous Host Control Register (Offset 0x68)” on page 204). When enabled, setting the mask bit of the Miscellaneous Host Control register will mask (de-assert) the INTA signal at the pin, but it will not clear the interrupt state and it will not latch the INTA value.
Page 245: Section 12: Bcm5722 Ethernet Controller Register Definitions
R e g i s t e r D e f in i t io n s Note: Unless specified otherwise, all registers and bit fields in this section are applicable to all the BCM5722 Ethernet controllers covered in this document.
Page 246 Power Management Data 0x50 Vital Product Data Capability ID 0x51 Next Capability Pointer (MSI) 0x52–0x53 VPD Address/Flag 0x54–0x57 VPD Data 0x58–0x5B Broadcom Vendor-Specific Capability Header 0x5C–05F Reset Counters 0x60–0x67 Reserved 0x68–0x6B Miscellaneous Host Control 0x6C–0x6F DMA Read/Write Control 0x70–0x73 PCI State 0x74–0x77...
Page 247 Programmer’s Guide BCM5722 10/15/07 Table 92: PCI Configuration Register Summary (Cont.) Offset Register 0xDA–0xDB Device Status 0xDC–0xDF Link Capabilities 0xE0–0xE1 Link Control 0xE2–0xE3 Link Status 0xE4–0xE7 Reserved 0xE8 MSI Capability ID 0xE9 Next Capability Pointer (null) 0xEA–0xEB MSI Control 0xEC–0xF3 MSI Address (64-bit) 0xF4–0xF7...
Page 248: Vendor Id Register (Offset 0X00)
EGISTER FFSET The 16-bit Vendor ID register identifies the manufacturer of the PCI adapter. Valid vendor identifiers are allocated by the PCI SIG to ensure uniqueness. Broadcom’s Vendor ID is 0x14E4. Table 93: Vendor ID Register (Offset 0x00) Field Description...
Page 249: Table 95: Command Register (Offset 0X04)
Enables palette snoop on VGA devices. This device does not support this capability, therefore, this bit is hardwired to Memory Write and The BCM5722 Ethernet controller does not support the Invalidate MWI command, therefore, this bit should remain cleared to Special Cycles Enables device to monitor Special Cycles operations.
Page 250: Table 96: Status Register (Offset 0X06)
BCM5722 Programmer’s Guide 10/15/07 TATUS EGISTER FFSET The 16-bit Status register is used to indicate status information to the PCI-based host for PCI bus-related events. All of the bit positions are predefined by the PCI specification. Not all bits in this register are implemented.
Page 251: Table 98: Class Code Register (Offset 0X09)
Programmer’s Guide BCM5722 10/15/07 LASS EGISTER FFSET The 24-bit Class Code register identifies the generic function of the device. All of the legal values are specific in the PCI specification. This field is hardwired to the class code for an Ethernet interface (0x020000).
Page 252: Table 102: Bist Register (Offset 0X0F)
BCM5722 Programmer’s Guide 10/15/07 BIST R EGISTER FFSET The 8-bit BIST register is used to initiate and report the results of any Built-In Self-Test. This device does not export BIST results to this register. Therefore, this register defaults to 0x00 at power-on reset. Optionally, firmware could be developed to execute a self-test and write the result into this register because this register may be written by the internal RISCs.
Page 253: Table 104: Subsystem Vendor Id Register (Offset 0X2C)
Table 105: Subsystem ID Register (Offset 0x2E) Field Description Init Access 15:0 Subsystem ID ID assigned by board manufacturer (BCM5722 MAC) 0x165A ID assigned by board manufacturer (BCM5755 MAC) 0x167B ID assigned by board manufacturer (BCM5755M MAC) 0x1673 ID assigned by board manufacturer (BCM5756M MAC)
Page 254: Table 106: Expansion Rom Base Address Register (Offset 0X30)
BCM5722 Programmer’s Guide 10/15/07 ROM B XPANSION DDRESS EGISTER FFSET The 32-bit Expansion ROM Base Address register is used to establish the location of Expansion ROM region within the device’s memory space. This ROM region is used for PXE support. The system software can determine how much address space the device requires by writing a value of all 1’s to the address portion of the register and then reading the value back.
Page 255: Table 109: Minimum Grant Register (Offset 0X3E)
Programmer’s Guide BCM5722 10/15/07 INIMUM RANT EGISTER FFSET This register does not apply to PCIe devices. Table 109: Minimum Grant Register (Offset 0x3E) Field Description Init Access Reserved – AXIMUM ATENCY EGISTER FFSET This register does not apply to PCIe devices.
Page 256: Table 111: Power Management Capability Register (Offset 0X48)
BCM5722 Programmer’s Guide 10/15/07 PCI P OWER ANAGEMENT APABILITIES Devices that support PCI Power Management must support a block of registers that is part of the Capabilities List in PCI Configuration Space. The PCI Power Management Register Block is located at offset 0x48. The device supports the following PCI Power Management registers.
Page 257: Table 114: Power Management Control/Status Register (Offset 0X4C)
Programmer’s Guide BCM5722 10/15/07 Table 113: Power Management Capabilities Register (Offset 0x4A) (Cont.) Field Description Init Access Aux Current The device supports the Data Register for reporting Aux Current requirements so this field is not applicable. Indicates that the device requires device specific initialization (beyond the PCI configuration header) before the generic class device driver is able to use it.
Page 258: Table 115: Power Management Data Register (Offset 0X4F)
BCM5722 Programmer’s Guide 10/15/07 OWER ANAGEMENT EGISTER FFSET This 8-bit register provides a mechanism for the device to report state dependent operating data such as power consumed or heat dissipation. Typically, the data returned through this register is a static copy of the device’s worst case DC characteristics data sheet.
Page 259: Table 116: Vpd Capability Id Register (Offset 0X50)
This register points to the next item in the Capabilities List. Table 117: VPD Next Capabilities Pointer Register (Offset 0x51) Field Description Init Access VPD Next Capabilities Points to the next capabilities block which is for Broadcom Vendor-Specific Capability Item. VPD F LAG AND DDRESS EGISTER...
Page 260: Table 119: Vpd Data Register (Offset 0X54)
BCM5722 Programmer’s Guide 10/15/07 VPD D EGISTER FFSET VPD data can be read through this register. Table 119: VPD Data Register (Offset 0x54) Field Description Init Access 31:0 VPD Data The least significant byte of the register corresponds to the byte of VPD at the address specified by the VPD Address register.
Page 261: Table 120: Msi Capability Id Register (Offset 0X58)
PCI-E Reset (Perst) Keeps track of number of PCIe Reset (Perst) Events Counter Link Down Reset Keeps track of number of Link Down Reset Events Counter Bro adco m Co rp or atio n Document 5722-PG101-R Broadcom Vendor-Specific Capabilities Page 202...
Page 262: Table 124: Device Serial No Lower Dw Override Register (Offset: 0X60)
Serial No. Upper DW Register at offset 0x168. When bit 23 of 0x7c04 is set to 0, the content of register 0x168 depends on the Upper MAC Address parameter from register 0x410. Bro adco m C orp or atio n Page 203 Broadcom Vendor-Specific Capabilities Document 5722-PG101-R...
Page 263: Table 126: Miscellaneous Host Control Register (Offset 0X68)
In that scenario, the interrupt will not be presented to INTA until this bit is cleared. Bro adco m Co rp or atio n Document 5722-PG101-R Broadcom Vendor-Specific Capabilities Page 204...
Page 264: Table 127: Dma Read/Write Control Register (Offset 0X6C)
• 2 = 96 • 3 = 128 • 4 = 160 • 5 = 192 • 6 = 224 • 7 = 256 18:0 Reserved – Bro adco m C orp or atio n Page 205 Broadcom Vendor-Specific Capabilities Document 5722-PG101-R...
Page 265: Table 128: Pci State Register (Offset 0X70)
Enable PCI ROM Base Address Register to be visible to the Desired PCI host. Reserved – PCI INT state Reflect the state of PCI INTA Reserved – a. Bit-enabled R/W through PCI configuration space. Bro adco m Co rp or atio n Document 5722-PG101-R Broadcom Vendor-Specific Capabilities Page 206...
Page 266: Table 129: Pci Clock Control Register
Slow Core Clock Mode Set this bit to 1 when running a 10:1 PCI to Core clock ratio. For engineering debug only. Reserved (BCM5906 only) – Bro adco m C orp or atio n Page 207 Broadcom Vendor-Specific Capabilities Document 5722-PG101-R...
Page 267 BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 only) Reserved (BCM5906 only) – Select Alt Clock (BCM5722, Uses the alternate clock as the clock reference for the BCM5755, BCM5755M, internal clocks, rather than the 62.5 MHz. In BCM5752, BCM5756M, BCM5757, this bit has no effect when TPM is enabled.
Page 268: Table 130: Register Base Address Register (Offset 0X78)
The least significant two bits of the Register Base Address register will always be ignored since Registers are naturally word (32-bit) aligned. To allow access to all of the BCM5722 Ethernet controller registers, the range of the Register Base Address register is [17:2].
Page 269: Table 131: Memory Window Base Address Register (Offset 0X7C)
The Memory Window Base Address register defines the device local memory address which is to be the base address for the 32 KB memory window provided by the BCM5722 Ethernet controller. This register may contain any valid local memory address, but the usage of the least significant 15 bits varies depending on how the local memory is to be accessed. If the 32 KB memory window is used, then the least significant 15 bits are ignored.
Page 270: Table 132: Register Data Register (Offset 0X80)
FFSET The Register Data register is used to access registers in the BCM5722 Ethernet controller. If this register is written to, the underlying register is also written. If this register is read, the current value of the underlying register is also read.
Page 271: Table 134: Expansion Rom Bar Size Register (0X88)
Programmer’s Guide BCM5722 10/15/07 ROM R XPANSION EGISTERS Note: Expansion ROM registers do not apply to the BCM5906 device. ROM BAR S XPANSION EGISTER FFSET Table 134: Expansion ROM BAR Size Register (0x88) Field Description Init Access 31:4 Reserved –...
Page 272: Table 136: Expansion Rom Data Register (0X90)
BCM5722 Programmer’s Guide 10/15/07 ROM D XPANSION EGISTER FFSET This register is for internal CPU use only. Table 136: Expansion ROM Data Register (0x90) Field Description Init Access 31:0 Data Expansion ROM Data. Loaded by the firmware after R/W–CPU executing the ROM read cycle.
Page 273: Table 138: Undi Receive Bd Standard Producer Ring Producer Index Mailbox (Offset 0X98)
Programmer’s Guide BCM5722 10/15/07 UNDI M AILBOX EGISTERS Note: UNDI Mailbox registers do not apply to the BCM5906 device. UNDI R BD S ECEIVE TANDARD RODUCER RODUCER NDEX AILBOX FFSET This is an alternate view of the Receive BD Standard Producer Ring Producer Index Mailbox from the mailboxes region. It is provided here to allow access from the PCI Configuration space.
Page 274: Table 141: Pcie Capability Id Register (Offset 0Xd0)
BCM5722 Programmer’s Guide 10/15/07 APABILITIES PCIe devices include new status and control registers that are located in the Capabilities List in the device's PCI Configuration Space. These PCIe capabilities registers start at offset 0xD0 of PCI Configuration Space. APABILITY EGISTER FFSET This eight-bit register identifies this item in the Capabilities List as a PCIe register set.
Page 275: Table 144: Device Capabilities Register (Offset 0Xd4)
Programmer’s Guide BCM5722 10/15/07 EVICE APABILITIES EGISTER FFSET This register defines operational characteristics that are globally applicable to this device. Table 144: Device Capabilities Register (Offset 0xD4) Field Description Init Access 31:28 Reserved – 27:26 Captured Slot Power This value specifies the scale used for the Power Limit.
Page 276: Table 145: Device Control Register (Offset 0Xd8)
BCM5722 Programmer’s Guide 10/15/07 Table 144: Device Capabilities Register (Offset 0xD4) (Cont.) Field Description Init Access Max Payload Size This value returns the maximum data payload size (in bytes) that this R/Wa Supported function supports for TLPs. • 0 = 128 •...
Page 277: Table 146: Device Status Register (Offset 0Xda)
Programmer’s Guide BCM5722 10/15/07 Table 145: Device Control Register (Offset 0xD8) (Cont.) Field Description Init Access Fatal Error Reporting When this bit is set, Fatal Error reporting is enabled. Enabled Non-fatal Error When this bit is set, Non-fatal Error reporting is Reporting Enable enabled.
Page 278: Table 147: Link Capabilities Register (Offset 0Xdc)
0: clkreq not capable • 0 for BCM5755, Host RO Management BCM5754, 1: clkreq capable FW R/W BCM5787, BCM5906, BCM5722, and BCM5757 • 1 for 5755M, BCM5754M, BCM5787M, BCM5906M, and BCM5756M 17:15 L1 Exit Latency This value returns the L1 exit latency for this link.
Page 279: Table 148: Link Control Register (Offset 0Xe0)
Programmer’s Guide BCM5722 10/15/07 ONTROL EGISTER FFSET Table 148: Link Control Register (Offset 0xE0) Field Description Init Access 15:9 Reserved – clkreq enable • 1 = Enable clkreq • 0 = Disable clkreq Extended Synch When this bit is set, it forces extended sync which gives external devices (such as logic analyzers) additional time to achieve bit and symbol lock.
Page 280: Table 150: Msi Capability Id Register (Offset 0Xe8)
BCM5722 Programmer’s Guide 10/15/07 ESSAGE IGNALED NTERRUPTS APABILITIES Devices that support Message Signaled Interrupts (MSI) must support a block of registers that is part of the Capabilities List in PCI Configuration Space. The MSI Register Block is located at offset 0xE8.
Page 281: Table 152: Message Control Register (Offset 0Xea)
Programmer’s Guide BCM5722 10/15/07 ESSAGE ONTROL EGISTER FFSET This 16-bit register provides system software control over MSI. After reset, MSI is disabled (bit 0 is cleared) and the function requests servicing via its INTA pin. System software can enable MSI by setting bit 0 of this register to a 1. System software is permitted to modify the Message Control register’s read/write bits and fields.
Page 282: Table 153: Message Address Register (Offset 0Xec)
BCM5722 Programmer’s Guide 10/15/07 ESSAGE DDRESS EGISTER FFSET This 64-bit register contains the system-specified message address. If the Message Enable bit (bit 0 of the Message Control Register) is set, the contents of this register specify a 32-bit aligned address for the MSI write transaction.
Page 283: Table 155: Advanced Error Reporting Enhanced Capability Header Register (Offset 0X100)
Programmer’s Guide BCM5722 10/15/07 NHANCED APABILITIES PCIe devices may optionally support a new configuration space that provides an additional 4 KB of configuration registers per device. This enhanced configuration space is mapped into host memory through a 256 MB window (enabled through the Root Complex) that provides access to the 4-KB enhanced configuration space for each of the 64K possible PCIe devices.
Page 284: Table 157: Uncorrectable Error Mask Register (Offset 0X108)
BCM5722 Programmer’s Guide 10/15/07 108) NCORRECTABLE RROR EGISTER FFSET Table 157: Uncorrectable Error Mask Register (Offset 0x108) Field Description Init Access 31:21 Reserved – Unsupported Request Setting this bit will mask Unsupported Request errors. Error Mask ECRC Error Mask Setting this bit will mask ECRC errors.
Page 285: Table 158: Uncorrectable Error Severity Register (Offset 0X10C)
Programmer’s Guide BCM5722 10/15/07 10C) NCORRECTABLE RROR EVERITY EGISTER FFSET Table 158: Uncorrectable Error Severity Register (Offset 0x10C) Field Description Init Access 31:21 Reserved – Unsupported Request This bit controls the severity when an Unsupported Request Error Error Severity occurs.
Page 286: Table 159: Correctable Error Status Register (Offset 0X110)
BCM5722 Programmer’s Guide 10/15/07 110) ORRECTABLE RROR TATUS EGISTER FFSET Table 159: Correctable Error Status Register (Offset 0x110) Field Description Init Access 31:13 Reserved – Replay Timer Timeout This bit is set when a Replay Timer Timeout error occurs. 0...
Page 287: Table 162: Virtual Channel Enhanced Capability Header (Offset 0X13C)
Programmer’s Guide BCM5722 10/15/07 Table 161: Advanced Error Capabilities and Control Register (Offset 0x118) (Cont.) Field Description Init Access First Error Pointer This value indicates the bit position within the “Uncorrectable Error Status Register (Offset 0x104)” on page 224 corresponding to the first error detected.
Page 288: Table 166: Port Vc Status Register (Offset 0X14A)
BCM5722 Programmer’s Guide 10/15/07 VC S 14A) TATUS EGISTER FFSET Table 166: Port VC Status Register (Offset 0x14A) Field Description Init Access VC Arbitration Table Status Not supported VC R 14C) ESOURCE APABILITY EGISTER FFSET Table 167: VC Resource Capability Register (Offset 0x14C)
Page 289: Table 170: Device Serial No Enhanced Capability Header Register (Offset 0X160)
Programmer’s Guide BCM5722 10/15/07 160) EVICE ERIAL NHANCED APABILITY EADER EGISTER FFSET Table 170: Device Serial No Enhanced Capability Header Register (Offset 0x160) Field Description Init Access 31:20 Next Capability Offset 0x16C when bit-6 of 0x7C04 is set to1 0x0 when bit-6 of 0x7C04 is set to 0 Reserved (BCM5906 only) –...
Page 290: Table 172: Device Serial No Upper Dw Register (Offset 0X168)
BCM5722 Programmer’s Guide 10/15/07 DW R 168) EVICE ERIAL PPER EGISTER FFSET Table 172: Device Serial No Upper DW Register (Offset 0x168) Field Description Init Access 31:8 Upper MAC Address This field is 0xFFFFFF after reset. 0xFFFFFF Config-RO If bit 23 of 0x7c04 is 1, this field is programmable...
Page 291: Table 175: Power Budgeting Data Register (Offset 0X174)
Programmer’s Guide BCM5722 10/15/07 174) OWER UDGETING EGISTER FFSET Table 175: Power Budgeting Data Register (Offset 0x174) Field Description Init Access 31:21 Reserved – 20:18 Power Rail Specifies the power rail of the operating condition RW from Internal CPU 12V (000) Config RO 3.3V (001)
Page 292: Table 177: Firmware Power Budgeting Register 1 (Offset 0X17C)
BCM5722 Programmer’s Guide 10/15/07 1 (O 17C) IRMWARE OWER UDGETING EGISTER FFSET Table 177: Firmware Power Budgeting Register 1 (Offset 0x17C) Field Description Init Access 15:13 Power Rail Specifies the power rail of the operating condition RW from Internal CPU...
Page 293: Table 179: Firmware Power Budgeting Register 3 (Offset 0X180)
Programmer’s Guide BCM5722 10/15/07 3 (O 180) IRMWARE OWER UDGETING EGISTER FFSET Table 179: Firmware Power Budgeting Register 3 (Offset 0x180) Field Description Init Access 15:13 Power Rail Specifies the power rail of the operating condition RW from Internal CPU...
Page 294: Table 181: Firmware Power Budgeting Register 5 (Offset 0X184)
BCM5722 Programmer’s Guide 10/15/07 5 (O 184) IRMWARE OWER UDGETING EGISTER FFSET Table 181: Firmware Power Budgeting Register 5 (Offset 0x184) Field Description Init Access 15:13 Power Rail Specifies the power rail of the operating condition RW from Internal CPU...
Page 295: Table 183: Firmware Power Budgeting Register 7 (Offset 0X188)
Programmer’s Guide BCM5722 10/15/07 7 (O 188) IRMWARE OWER UDGETING EGISTER FFSET Table 183: Firmware Power Budgeting Register 7 (Offset 0x188) Field Description Init Access 15:13 Power Rail Specifies the power rail of the operating condition RW from Internal CPU...
Page 296: Table 185: Pcie 1.1 Advisory Non-Fatal Error Masking (Offset: 0X18C)
BCM5722 Programmer’s Guide 10/15/07 1.1 A 18C) DVISORY ATAL RROR ASKING FFSET Table 185: PCIe 1.1 Advisory Non-Fatal Error Masking (Offset: 0x18C) Field Description Init Reset Access 31:6 Reserved – Retry Poison Enable DMA Read Engine to retry poison PCI_Reset...
Page 297: Table 186: High-Priority Mailbox Registers
Programmer’s Guide BCM5722 10/15/07 RIORITY AILBOXES Note: High-Priority Mailboxes do not exist in the BCM5906 device. These registers are called High-Priority Mailbox registers (or high-priority mailboxes). When a value is stored in the least significant 32 bits of these registers, an event (known as a high-priority mailbox event) is generated to the RX RISC. To write 64 bits of a mailbox location, the upper 32 bits should be written to before the lower 32 bits.
Page 298 • Whenever In_ISR bits in this register contain a nonzero value, it indicates to the BCM5722 Ethernet controller that host software is in its interrupt processing routine (ISR). This causes the device to use the during interrupt coalescing registers as opposed to the non-during interrupt coalescing registers.
Page 299 EGISTER FFSET This register is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, and BCM5757 devices only. The Receive BD Return Ring Index register contains the index of last the buffer descriptor for return ring 4 that has been consumed. Host software writes this register whenever it updates the return ring 4. This register must be initialized to 0.
Page 300: Table 188: Ethernet Mac Control Registers-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757
EGISTERS These registers are used to control the operation of the Ethernet MAC. There are several parameters which are available for performance and compatibility tuning. Table 188: Ethernet MAC Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Offset Registers Init 0x400–0x403...
Page 301 Programmer’s Guide BCM5722 10/15/07 Table 188: Ethernet MAC Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only (Cont.) Offset Registers Init 0x488–0x48b Recv BD Rules Control Register 1 0x00000000 0x48c–0x48f Recv BD Rules Mask/Value Register 1 0x00000000 0x490–0x493 Recv BD Rules Control Register 2 0x00000000 0x494–0x497...
Page 302: Table 189: Ethernet Mac Control Registers-Bcm5906 Only
BCM5722 Programmer’s Guide 10/15/07 Note: The EMAC debug register (0x8F0) below is R/O. A read to the debug register returns the internal state value. Table 189: Ethernet MAC Control Registers—BCM5906 Only Offset Registers Init 0x400–0x403 Ethernet MAC Mode 0x00000004 0x404–0x407...
Page 303 Programmer’s Guide BCM5722 10/15/07 Table 189: Ethernet MAC Control Registers—BCM5906 Only (Cont.) Offset Registers Init 0x518–0x51f Reserved 0x520–0x52f Mac Hash Table Register 0x530–0x5ff Reserved 0x600–0x620 EMAC internal state debugging registers 0x623–0x62f Reserved 0x630–0x66f Indirection Table Registers 0–15 0x670–0x697 Hash Key Registers 0–9 0x698–0x69f...
Page 304: Table 190: Ethernet Mac Mode Register (Offset 0X400)
BCM5722 Programmer’s Guide 10/15/07 MAC M 400) THERNET EGISTER FFSET Table 190: Ethernet MAC Mode Register (Offset 0x400) Field Description Init Access 31:27 Reserved – Free Running ACPI When this bit is set, the ACPI state machine will continue running when a match is found. When this bit is clear, the ACPI state machine will halt when a match is found.
Page 305: Table 191: Ethernet Mac Status Register (Offset 0X404)
Programmer’s Guide BCM5722 10/15/07 MAC S 404) THERNET TATUS EGISTER FFSET Table 191: Ethernet MAC Status Register (Offset 0x404) Field Description Init Access 31:29 Reserved Always 0. Interesting Packet PME When this bit is set, the WOL signal is asserted when Attention an interesting packet is detected.
Page 306: Table 192: Ethernet Mac Event Enable Register (Offset 0X408)
BCM5722 Programmer’s Guide 10/15/07 MAC E 408) THERNET VENT NABLE EGISTER FFSET Table 192: Ethernet MAC Event Enable Register (Offset 0x408) Field Description Init Access 31:29 Reserved Always 0. Interesting Packet PME When this bit is set, an attention will be asserted on an interesting packet Attention Enable match.
Page 307 Programmer’s Guide BCM5722 10/15/07 Table 193: LED Control Register (Offset 0x40C) (Cont.) Field Description Init Access 12:11 LED_MODE • 00 = MAC Mode—LED signal is in active low (on) when link is established and is in high (off) when link is not established.
Page 308: Table 194: Ethernet Mac Address High Register (Offset 0X410)
BCM5722 Programmer’s Guide 10/15/07 Table 193: LED Control Register (Offset 0x40C) (Cont.) Field Description Init Access Note: To enable either MAC Mode or Shared Traffic/Link LED Mode, the LED Mode (bits 12:11) must be set to MAC LED mode (0x0).
Page 309: Table 197: Wol Pattern Configuration Register (Offset 0X434)
Programmer’s Guide BCM5722 10/15/07 WOL P 434) ATTERN ONFIGURATION EGISTER FFSET Table 197: WOL Pattern Configuration Register (Offset 0x434) Field Description Init Access 31:28 Reserved – 27:16 ACPI offset Offset of a frame where the pattern comparison starts. 15:10 Reserved –...
Page 310: Table 200: Mi Communication Register (Offset 0X44C)
BCM5722 Programmer’s Guide 10/15/07 MI C 44C) OMMUNICATION EGISTER FFSET This register is used to communicate with a transceiver device through the MII/GMII management interface signals MDIO and MDC. To complete a transaction, the register values are configured for the operation, and the Start bit (bit 29) is set.
Page 311: Table 202: Mi Mode Register (Offset 0X454)
Programmer’s Guide BCM5722 10/15/07 MI M 454) EGISTER FFSET This register controls autopolling on the management interface. Auto control mode sets the link state in the transmit state register. Table 202: MI Mode Register (Offset 0x454) Field Description Init Access...
Page 312: Table 204: Transmit Mac Mode Register (Offset 0X45C)
Reserved – Tx MAC State Machine Set this bit to 1 to enable the chip fix of Tx MAC FSM Lockup Fix Enable Lockup Issue that happens due to corrupted TxMbuf. (BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757 only) Reserved (other –...
Page 313: Table 206: Transmit Mac Lengths Register (Offset 0X464)
Any combinations of hash types are supported. Reserved (other devices) – 22:20 RSS Hash Mask Bits (BCM5722, These bits specify the number of hash bits that are used to BCM5755, BCM5755M, offset into the indirection table. A value of one specifies BCM5756M, BCM5757 only)
Page 314 IPv6 packets. This bit should be set to 0 if IPv6 RX is BCM5756M, BCM5757 only) disabled. Reserved (other devices) RSS IPv6 Hash Enable (BCM5722, When this bit is set, 2-tuple hashes are enabled for IPv6 BCM5755, BCM5755M, packets. This bit should be set to 0 if IPv6 RX is disabled.
Page 315: Table 208: Receive Mac Status Register (Offset 0X46C)
Programmer’s Guide BCM5722 10/15/07 MAC S 46C) ECEIVE TATUS EGISTER FFSET This register contains the status of the receive Ethernet interface. Once the interface is initialized, this register is used to determine the cause of a receive error event. Table 208: Receive MAC Status Register (Offset 0x46C)
Page 316: Table 210: Receive Rules Control Register (Offset 0X480)
ONTROL EGISTERS FFSET The BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5787, BCM5787M, BCM5754, and BCM5754M MACs implement eight receive rules (N = 0 to 7) only. Note: Receive Rules Control Registers do not apply to the BCM5906 device. Table 210: Receive Rules Control Register (Offset 0x480)
Page 317: Table 211: Receive Rules Value/Mask Register (Offset 0X484)
31:21 Reserved Reserved. 20:16 Tx FIFO Almost Empty When the remaining entries of Tx FIFO are less than this Threshold (BCM5722, threshold, the TXFIFO_Almost_Empty will be asserted. BCM5755, This value is used in conjunction with the bit-31 of “Buffer BCM5755M, Manager Mode Register (Offset 0x4400)”...
Page 318: Table 214: Ethernet Type Matching Value Register (Offset 0X510)
Programmer’s Guide 10/15/07 Note: The BCM5722 Ethernet controller generates a pause frame when the Low Watermark Max Receive Frames value has been reached. When a pause frame has been generated, the TX data path also stalls (assuming it has not already reached the value specified by the “Read DMA MBUF Low Watermark Register (Offset 0x4410)”...
Page 319: Table 216: Regulator Voltage Control Register (Offset 0X590)
Programmer’s Guide BCM5722 10/15/07 590) EGULATOR OLTAGE ONTROL EGISTER FFSET This register is applicable to BCM5906, BCM5906M, BCM5787, and BCM5787M devices only. Table 216: Regulator Voltage Control Register (Offset 0x590) Field Description Init Access 31:28 Reserved – 27:24 Regctl 2.5V Output voltage trim control.
Page 320: Table 217: Indirection Table Register 0 (Offset: 0X630)
Programmer’s Guide 10/15/07 0 (O 630) NDIRECTION ABLE EGISTER FFSET This register is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, and BCM5757 devices only. Table 217: Indirection Table Register 0 (Offset: 0x630) Field Description Init Access 31:28 table_entry0 The RSS_ring value for entry 0. Only the least significant 2 bits are used.
Page 321: Table 218: Indirection Table Register 15 (Offset: 0X66C)
BCM5722 10/15/07 15 (O 66C) NDIRECTION ABLE EGISTER FFSET This register is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, and BCM5757 devices only. Table 218: Indirection Table Register 15 (Offset: 0x66C) Field Description Init Access 31:28 table_entry120 The RSS_ring value for entry 120. Only the least significant 2 bits are used.
Page 322: Table 220: Hash Key Register 9 (Offset: 0X694)
BCM5722 Programmer’s Guide 10/15/07 9 (O 694) EGISTER FFSET This register is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, and BCM5757 devices only. Table 220: Hash Key Register 9 (Offset: 0x694) Field Description Init Access 31:24 Hash_key[295:288] The thirty-seventh byte of the hash_key. The bits are in the big...
Page 323: Table 222: Statistics Registers
Programmer’s Guide BCM5722 10/15/07 TATISTICS EGISTERS Note: The statistics registers are automatically cleared (reset to zero) upon read. Table 222: Statistics Registers Address Length Description 0x0800–0x0803 bits 0:27 TX MAC Statistic Counter—ifHCOutOctets 0x0804–0x0807 Reserved 0x0808–0x080b bits 0:16 TX MAC Statistic Counter—etherStatsCollisions 0x080c–0x080f...
Page 324 BCM5722 Programmer’s Guide 10/15/07 Table 222: Statistics Registers Address Length Description 0x08bc–0x8ff Reserved MAC S RANSMIT TATISTIC OUNTERS ifHCOutOctets (Offset 0x0800) The number of octets transmitted out of the interface, including framing characters. etherStatsCollisions (Offset 0x0808) The number of collisions experienced.
Page 325 Programmer’s Guide BCM5722 10/15/07 ifHCOutMulticastPkts (Offset 0x0870) The number of packets that higher-level protocols requested be transmitted, and that were addressed to a multicast address at this sublayer, including those that were discarded or not sent. ifHCOutBroadcastPkts (Offset 0x0874) The number of packets that higher-level protocols requested be transmitted, and that were addressed to a broadcast address at this sublayer, including those that were discarded or not sent.
Page 326 BCM5722 Programmer’s Guide 10/15/07 xoffPauseFramesReceived (Offset 0x08A4) MAC control frames with pause command and length greater than zero. macControlFramesReceived (Offset 0x08A8) MAC control frames with no pause command. xoffStateEntered (Offset 0x08AC) Transmitting is disabled. dot3StatsFramesTooLongs (Offset 0x08B0) A count of frames received on a particular interface that exceeds the maximum permitted frame size.
Page 327: Table 223: Send Data Initiator Control Registers-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only
Programmer’s Guide BCM5722 10/15/07 NITIATOR ONTROL EGISTERS Table 223: Send Data Initiator Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Offset Registers 0x0c00–0x0c03 Send Data Initiator Mode 0x0c04–0x0c07 Send Data Initiator Status 0x0c08–0x0c0b Send Data Initiator Statistics Control 0x0c0c–0x0c0f Send Data Initiator Statistics Enable Mask 0x0c10–0x0c13...
Page 328: Table 225: Send Data Initiator Mode Register (Offset 0X0C00)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only
BCM5722 Programmer’s Guide 10/15/07 0C00)—BCM5722, BCM5755, NITIATOR EGISTER FFSET BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787, BCM5906 O Table 225: Send Data Initiator Mode Register (Offset 0x0C00)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description Init Access 31:5 Reserved – Pre-DMA Debug Enable When this bit is set, the Send Data Initiator state machine is halted when the pre-DMA bit of the Send BD is set.
Page 329: Table 227: Send Data Initiator Status Register (Offset 0X0C04)
Programmer’s Guide BCM5722 10/15/07 0C04) NITIATOR TATUS EGISTER FFSET Table 227: Send Data Initiator Status Register (Offset 0x0C04) Field Description Init Access 31:3 Reserved – Stats Overflow Attn A statistics managed by Send Data Initiator has overflowed. Reserved – 0C08)
Page 330: Table 230: Send Data Initiator Statistics Increment Mask Register (Offset 0X0C10)
BCM5722 Programmer’s Guide 10/15/07 0C10) NITIATOR TATISTICS NCREMENT EGISTER FFSET Table 230: Send Data Initiator Statistics Increment Mask Register (Offset 0x0C10) Field Description Init Access 31:24 Reserved – 23:19 Counters Increment Writing a 1 to the bit position forces the corresponding statistics counter Mask to increment by 1.
Page 331: Table 233: Logged Local Network Time For Inbound/Outbound Time Sync Packet (Offset 0X0C28-0X0C2B)-Bcm5906 Only
Programmer’s Guide BCM5722 10/15/07 OGGED OCAL ETWORK NBOUND UTBOUND ACKET FFSET 0C28–0 0C2B)—BCM5906 O Note: Both TX and RX time-sync packet timestamps share the same timestamp register at offset 0xc28. Table 233: Logged Local Network Time for Inbound/Outbound Time Sync Packet (Offset 0x0C28–0x0C2B)—BCM5906 Only...
Page 332: Table 235: Tcp Segmentation Control Registers
BCM5722 Programmer’s Guide 10/15/07 TCP S EGMENTATION ONTROL EGISTERS Table 235: TCP Segmentation Control Registers Offset Registers 0x0ce0–0x0ce3 Lower Host Address Register for TCP Segmentation 0x0ce4–0x0ce7 Upper Host Address Register for TCP Segmentation 0x0ce8–0x0ceb Length/Offset Register for TCP Segmentation 0x0cec–0x0cef DMA Flags Register for TCP Segmentation 0x0cf0–0x0cf3...
Page 333: Table 239: Dma Flags Register For Tcp Segmentation (Offset 0Xcec)
Programmer’s Guide BCM5722 10/15/07 DMA F TCP S CEC) LAGS EGISTER FOR EGMENTATION FFSET Table 239: DMA Flags Register for TCP Segmentation (Offset 0xCEC) Field Description Init Access 31:20 Reserved – MBUF offset valid MBUF offset valid. When this bit is set, the RDMA engine will DMA the data...
Page 334: Table 240: Vlan Tag Register For Tcp Segmentation (Offset 0Xcf0)
BCM5722 Programmer’s Guide 10/15/07 Table 239: DMA Flags Register for TCP Segmentation (Offset 0xCEC) (Cont.) Field Description Init Access Invoke Processor Invoke Processor. Clear the PASS bit of the entry queued to the SDCQ, so that SDC will invoke the CPU.
Page 335: Table 242: Send Data Completion Control Registers
Programmer’s Guide BCM5722 10/15/07 OMPLETION ONTROL EGISTERS Table 242: Send Data Completion Control Registers Offset Registers 0x1000–0x1003 Send Data Completion Mode. 0x1004–0x1007 Reserved. 0x1008–0x100B Post-DMA Command Exchange for TCP Segmentation 0x100C–0x13FF Reserved. 1000) OMPLETION EGISTER FFSET Table 243: Send Data Completion Mode Register (Offset 0x1000)
Page 336: Table 245: Send Bd Ring Selector Control Registers
BCM5722 Programmer’s Guide 10/15/07 BD R ELECTOR ONTROL EGISTERS The following registers may be used by software for debug and diagnostic purposes. For example, Host software could compare the Send BD Consumer Index located in the Status block (see “Status Block” on page 53) to the registers located in this region.
Page 337: Table 248: Send Bd Diagnostic Ring Selector Local Nic Send Bd Consumer Index Registers (Offset 0X1440)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only
EGISTER 1440–0 1444)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, FFSET BCM5754, BCM5787 O Table 248: Send BD Diagnostic Ring Selector Local NIC Send BD Consumer Index Registers (Offset 0x1440)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description Init Access 31:9 Reserved –...
Page 338: Table 250: Send Bd Ring Selector Control Registers
BCM5722 Programmer’s Guide 10/15/07 BD I NITIATOR ONTROL EGISTERS These registers are available for diagnostic and debug purposes. For example, host software may compare the value written to the high priority mailbox region (see “High-Priority Mailboxes” on page 238) against the value the MAC processes located in the Send BD Initiator Control register region.
Page 339: Table 253: Send Bd Completion Control Registers
Programmer’s Guide BCM5722 10/15/07 BD C OMPLETION ONTROL EGISTERS Table 253: Send BD Completion Control Registers Offset Registers 0x1c00–0x1c03 Send BD Completion Mode. 0x1c04–0x1fff Reserved. BD C 1C00) OMPLETION EGISTER FFSET Table 254: Send BD Completion Mode Register (Offset 0x1C00)
Page 340: Table 255: Receive List Placement Control Registers-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only
BCM5722 Programmer’s Guide 10/15/07 ECEIVE LACEMENT ONTROL EGISTERS Table 255: Receive List Placement Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Offset Registers 0x2000–0x2003 Receive List Placement Mode 0x2004–0x2007 Receive List Placement Status 0x2008–0x200f Reserved 0x2010–0x2013 Receive List Placement Configuration Register 0x2014–0x2017...
Page 341: Table 257: Receive List Placement Mode Register (Offset 0X2000)
Programmer’s Guide BCM5722 10/15/07 Table 256: Receive List Placement Control Registers—BCM5906 Only (Cont.) Offset Registers 0x2204–0x223f Reserved 0x2240–0x2243 Local Statistics Counter—Drop Due to Filter 0x2244–0x2247 Local Statistics Counter—DMA Write Queue Full 0x2248–0x224b Local Statistics Counter—DMA High Priority Write Queue Full 0x224c–0x224f...
Page 342: Table 259: Receive List Placement Configuration Register (Offset 0X2010)
BCM5722 Programmer’s Guide 10/15/07 2010) ECEIVE LACEMENT ONFIGURATION EGISTER FFSET Table 259: Receive List Placement Configuration Register (Offset 0x2010) Field Description Init Access 31:15 Reserved – 14:13 Default Interrupt Default interrupt distribution queue. Number within a class Distribution Queue of service group when the frame has errors, is truncated, or is a non-IP frame.
Page 343: Table 261: Receive List Placement Statistics Enable Mask Register (Offset 0X2018)
Init Access 31:26 Reserved – RSS_Priority (BCM5722, This bit enables the receive packet to choose receive return ring BCM5755, BCM5755M, in terms of RSS hash value instead of RC class when both RSS BCM5756M, BCM5757 only) and RC rules are matched. Default is to give priority to RC.
Page 344: Table 262: Receive List Placement Statistics Increment Mask Register (Offset 0X201C)
BCM5722 Programmer’s Guide 10/15/07 201C) ECEIVE LACEMENT TATISTICS NCREMENT EGISTER FFSET Table 262: Receive List Placement Statistics Increment Mask Register (Offset 0x201C) Field Description Init Access 31:22 Reserved – 21:16 Counters Increment Mask Writing a 1 to a Counters Increment Mask bit forces the corresponding statistics counter to increment by 1.
Page 345: Table 264: Receive Data And Receive Bd Initiator Control Registers
Programmer’s Guide BCM5722 10/15/07 BD I ECEIVE ATA AND ECEIVE NITIATOR ONTROL EGISTERS Table 264: Receive Data and Receive BD Initiator Control Registers Offset Registers 0x2400–0x2403 Receive Data and Receive BD Ring Initiator Mode 0x2404–0x2407 Receive Data and Receive BD Ring Initiator Status 0x2408–0x244f...
Page 346: Table 266: Receive Data And Receive Bd Initiator Status Register (Offset 0X2404)
BCM5722 Programmer’s Guide 10/15/07 BD I 2404) ECEIVE ATA AND ECEIVE NITIATOR TATUS EGISTER FFSET Table 266: Receive Data and Receive BD Initiator Status Register (Offset 0x2404) Field Description Init Access 31:5 Reserved – Illegal return ring size One of the return rings contains illegal ring size (e.g., only contains...
Page 347: Table 271: Receive Data Completion Control Registers
Programmer’s Guide BCM5722 10/15/07 BD R NIC S ECEIVE IAGNOSTIC ATA AND ECEIVE NITIATOR OCAL TANDARD BD C 2474) ECEIVE ONSUMER NDEX FFSET The NIC local copy of Standard Receive Producer Ring Consumer Index. BD I ECEIVE ATA AND ECEIVE...
Page 348: Table 273: Receive Bd Initiator Control Registers
BCM5722 Programmer’s Guide 10/15/07 BD I ECEIVE NITIATOR ONTROL EGISTERS Table 273: Receive BD Initiator Control Registers Offset Registers 0x2c00–0x2c03 Receive BD Initiator Mode 0x2c04–0x2c07 Receive BD Initiator Status 0x2c08–0x2c0b Reserved 0x2c0c–0x2c0f Receive BD Initiator Local NIC Standard Receive BD Producer Index 0x2c10–0x2c17...
Page 349: Table 276: Standard Receive Bd Producer Ring Replenish Threshold Register (Offset 0X2C18)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only
The value programmed in this register indicates the number of buffer descriptors that must be indicated before a DMA is initiated. Table 276: Standard Receive BD Producer Ring Replenish Threshold Register (Offset 0x2C18)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only...
Page 350: Table 278: Receive Bd Completion Control Registers
BCM5722 Programmer’s Guide 10/15/07 BD C ECEIVE OMPLETION ONTROL EGISTERS Table 278: Receive BD Completion Control Registers Offset Registers 0x3000–0x3003 Receive BD Completion Mode 0x3004–0x3007 Receive BD Completion Status 0x3008–0x300b Reserved 0x300c–0x300f NIC Standard Receive BD Producer Index 0x3010–0x37ff Reserved...
Page 351: Host Coalescing Control Registers
Host Coalescing state machine always updates the host on frame boundaries. Additionally, the Host Coalescing state machine regulates the rate at which the statistics are updated in host memory. Table 282: Host Coalescing Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only...
Page 352 BCM5722 Programmer’s Guide 10/15/07 Table 283: Host Coalescing Control Registers—BCM5906 Only (Cont.) Offset Registers 0x3c18–0x3c1f Reserved 0x3c20–0x3c23 Receive Max Coalesced BD Count, during Interrupt 0x3c24–0x3c27 Send Max Coalesced BD Count, during Interrupt 0x3c28–0x3c37 Reserved 0x3c38–0x3c3f Status Block Host Address 0x3c40–0x3c43 Reserved 0x3c44–0x3c47...
Page 353: Host Coalescing Mode Register (Offset 0X3C00)
Programmer’s Guide BCM5722 10/15/07 3C00) OALESCING EGISTER FFSET Table 284: Host Coalescing Mode Register (Offset 0x3C00) Field Description Init Access 31:13 Reserved – No Interrupt on Force When set, writing the Coalesce Now bit will cause a Update status block update without a corresponding interrupt event.
Page 354: Host Coalescing Status Register (Offset 0X3C04)
BCM5722 Programmer’s Guide 10/15/07 3C04) OALESCING TATUS EGISTER FFSET Table 285: Host Coalescing Status Register (Offset 0x3C04) Field Description Init Access 31:3 Reserved – Error Host Coalescing error status. Reserved – 3C08) ECEIVE OALESCING ICKS EGISTERS FFSET The value in this register can be used to control how often the status block is updated (and how often interrupts are generated) due to receiving packets.
Page 355: Receive Max Coalesced Bd Count (Offset 0X3C10)
Programmer’s Guide BCM5722 10/15/07 their send buffers to be freed quickly. For host environments that do require their send buffers to be recovered quickly, it is recommended that this register be set to 0. BD C 3C10) ECEIVE OALESCED OUNT...
Page 356: Receive Max Coalesced Bd Count During Interrupt (Offset 0X3C20)
BCM5722 Programmer’s Guide 10/15/07 BD C 3C20) ECEIVE OALESCED OUNT URING NTERRUPT FFSET This register is similar to “Receive Max Coalesced BD Count (Offset 0x3C10)” on page 296, but it is used instead when the host is considered to be in its interrupt service routine (ISR). In this case, the NIC considers the host to be in its ISR whenever “Interrupt Mailbox 0 Register (Offset 0x200–0x207)”...
Page 357: Nic Receive Bd Consumer Index Register (Offset 0X3C54-0X3C57)
Note: The programmer should not write to these registers—they are for internal use to aid with debugging and diagnostics only. Table 287: NIC Return Ring Producer Index Registers (Offset 0x3C80, 0x3c84, 0x3c88, and 0x3c8c)— BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description...
Page 358: Nic Diagnostic Return Rings Producer Index Register (Offset 0X3C80-0X3C83)-Bcm5906 Only
BCM5722 Programmer’s Guide 10/15/07 NIC D IAGNOSTIC ETURN INGS RODUCER NDEX EGISTER FFSET 3C80–0 3C83)—BCM5906 O This register keeps track of the NIC local copy of the return ring producer index (not the host copy which is DMAed by the Host Coalescing engine to the host).
Page 359: Nic Diagnostic Send Bd Consumer Index Register (Offset 0X3Cc0-0X3Cc3)
Host Coalescing engine to the host). This is shared between the Send BD Initiator and the Host Coalescing state machines. Note: The programmer should not write to this register—it is for internal use only to aid with debugging and diagnostics. Table 289: NIC Send BD Consumer Index (Offset 0x3CC0)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description...
Page 360: Memory Arbiter Registers
BCM5722 Programmer’s Guide 10/15/07 EMORY RBITER EGISTERS Table 291: Memory Arbiter Registers Offset Registers 0x4000–0x4003 Memory Arbiter Mode 0x4004–0x4007 Memory Arbiter Status. Reserved in BCM5906 0x4008–0x400b Memory Arbiter Trap Address Low Reserved in BCM5906 0x400c–0x400f Memory Arbiter Trap Address High Reserved in BCM5906 0x4010–0x43ff...
Page 361 Programmer’s Guide BCM5722 10/15/07 Table 292: Memory Arbiter Mode Register (Offset 0x4000) (Cont.) Field Description Init Access RQ Addr Trap Enable Receive List Placement Memory Arbiter request trap enable. Reserved (BCM5906 only) – Reserved – PCI Addr Trap Enable PCI Memory Arbiter request trap enable.
Page 362: Bcm5757, Bcm5754, Bcm5787 Only
Reserved – 4008)—BCM5722, EMORY RBITER DDRESS EGISTER FFSET BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 O Table 294: Memory Arbiter Trap Address Low Register (Offset 0x4008)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description Init Access 31:21 Reserved – 20:0 MA Trap Addr Low Memory Arbiter Trap Address Low.
Page 363: Memory Arbiter Trap Address High Register (Offset 0X400C)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only
BCM5722 10/15/07 400C)—BCM5722, EMORY RBITER DDRESS EGISTER FFSET BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 O Table 295: Memory Arbiter Trap Address High Register (Offset 0x400C)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description Init Access 31:21 Reserved – 20:0 MA Trap Addr High Memory Arbiter Trap Address High.
Page 364: Buffer Manager Control Registers
BCM5722 Programmer’s Guide 10/15/07 UFFER ANAGER ONTROL EGISTERS Table 296: Buffer Manager Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Offset Registers 0x4400–0x4403 Buffer Manager Mode register 0x4404–0x4407 Buffer Manager Status register 0x4408–0x440b MBUF pool base address 0x440c–0x440f MBUF pool length 0x4410–0x4413...
Page 365: Buffer Manager Mode Register (Offset 0X4400)
4404) UFFER ANAGER TATUS EGISTER FFSET Note: This register is not applicable to the BCM5906 device. Table 299: Buffer Manager Status Register (Offset 0x4404)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description Init Access 31:5 BM Test Mode –...
Page 366: Mbuf Pool Base Address Register (Offset 0X4408)
BCM5722 Programmer’s Guide 10/15/07 MBUF P 4408) DDRESS EGISTER FFSET Note: This register is not applicable to the BCM5906 device. The MBUF Pool Base Address specifies beginning of the MBUF. Table 300: MBUF Pool Base Address Register (Offset 0x4408) Field...
Page 367: Mac Rx Mbuf Low Watermark Register (Offset 0X4414)
Programmer’s Guide BCM5722 10/15/07 MAC RX MBUF L 4414) ATERMARK EGISTER FFSET This 32-bit register indicates the number of free MBUFs that must be available for the RX MAC to accept a frame. If the free MBUF count drops below this mark, it must go above the high watermark to resume normal operation.
Page 368: Rx Risc Mbuf Allocation Response Register (Offset 0X4420)
BCM5722 Programmer’s Guide 10/15/07 RX RISC MBUF A 4420) LLOCATION ESPONSE EGISTER FFSET Note: This register is not applicable to the BCM5906 device. This register returns the MBUF cluster pointer of the specified size when the Allocation bit is cleared. If a second MBUF cluster allocation request is made before this register is read, an MBUF memory leak may occur.
Page 369: Bm Hardware Diagnostic 3 Register (Offset 0X4454)
Programmer’s Guide BCM5722 10/15/07 BM H 4454) ARDWARE IAGNOSTIC EGISTER FFSET This 32-bit register provides debug information on the RXMBUF pointer. Table 305: BM Hardware Diagnostic 3 Register (Offset 0x4454) Field Description Init Access 31:25 Reserved – 0000000 24:16 Next RXMBUF The next RXMBUF that is to be deallocated.
Page 370: Read Dma Control Registers
BCM5722 Programmer’s Guide 10/15/07 DMA C ONTROL EGISTERS Table 307: Read DMA Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Offset Registers 0x4800–0x4803 Read DMA Mode 0x4804–0x4807 Read DMA Status 0x4808–0x4bff Reserved Note: For the BCM5906 device only, the RDMA “debug” registers listed are all read-only. Reads to these registers return internal state values.
Page 371 Programmer’s Guide BCM5722 10/15/07 Table 309: Read DMA Mode Register (Offset 0x4800) (Cont.) Field Description Init Access Address Overflow Error Logging This bit when set, enables the address overflow error to Enable be generated when the DMA Read Engine performs a DMA operation that crosses a 4G boundary.
Page 372: Read Dma Status Register (Offset 0X4804)
BCM5722 Programmer’s Guide 10/15/07 DMA S 4804) TATUS EGISTER FFSET Table 310: Read DMA Status Register (Offset 0x4804) Field Description Init Access 31:11 Reserved – Read DMA PCI-X Split Transaction Read DMA PCI-X split transaction timeout expired. Timeout Expired Read DMA Local Memory Write...
Page 373: Write Dma Control Registers
Programmer’s Guide BCM5722 10/15/07 DMA C RITE ONTROL EGISTERS Table 312: Write DMA Control Registers Offset Registers 0x4c00–0x4c03 Write DMA Mode 0x4c04–0x4c07 Write DMA Status 0x4c08–0x4c4c WDMA debug register 0–18 (BCM5906 only) 0x4c4f–0x4fff Reserved Note: The BCM5906 WDMA debug register is read-only. Reads to this register return the internal state value. Do not write to this register.
Page 374: Write Dma Status Register (Offset 0X4C04)
BCM5722 Programmer’s Guide 10/15/07 Table 313: Write DMA Mode Register (Offset 0x4C00) (Cont.) Field Description Init Access Write DMA Local Memory Attention Enable. Enable Write DMA Local Memory Read Read Longer Than DMA Longer Than DMA Length Attention. Length Write DMA PCI FIFO...
Page 375 Programmer’s Guide BCM5722 10/15/07 Table 314: Write DMA Status Register (Offset 0x4C04) (Cont.) Field Description Init Access Write DMA PCI Parity Write DMA PCI Parity Error. Error Write DMA PCI Master Write DMA PCI Master Abort Error. Abort Error Write DMA PCI Target Write DMA PCI Target Abort Error.
Page 376: Rx Risc Registers
BCM5722 Programmer’s Guide 10/15/07 RX RISC R EGISTERS Note: RX RISC registers are not applicable to the BCM5906 device. The following RX RISC registers are exposed to host software to provide a mechanism to download firmware binary. The information in this section is not intended to provide a comprehensive understanding of the RISC architecture.
Page 377: Rx Risc State Register (Offset 0X5004)
Programmer’s Guide BCM5722 10/15/07 Table 316: RX RISC Mode Register Fields (Offset 0x5000) (Cont.) Field Description Init Access Enable Watchdog Enables watchdog interrupt state machine. Used in conjunction with Watchdog Clear register, Watchdog Saved PC register and Watchdog Vector register.
Page 378 BCM5722 Programmer’s Guide 10/15/07 Table 317: RX RISC State Fields (Offset 0x5004) (Cont.) Field Description Init Access MA outstanding read MA_rd_FIFO overflowed. The RX RISC is halted on this FIFO overflow condition. MA outstanding write MA_wr_FIFO overflowed. The RX RISC is halted on this FIFO overflow condition.
Page 379: Rx Risc Program Counter (Offset 0X501C)
Programmer’s Guide BCM5722 10/15/07 RX RISC P 501C) ROGRAM OUNTER FFSET The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline.
Page 380: Virtual Cpu Registers (Bcm5906 Only)
This bit is cleared on a hard reset. Note : The driver needs to set this bit to “1” before issuing a GRC or VCPU reset. Combining with bit 26, the driver can communicate with the Broadcom device on the reset/init sequence. Init Done Indicates to the host that the VCPU has finished the initialization and the host can start the driver loading.
Page 381: Device Configuration Shadow Register (Offset 0X5104)
Programmer’s Guide BCM5722 10/15/07 Table 321: VCPU Status Register Fields (Offset 0x5100) Field Description Init Access VCPU Int All CPU attention bits are ORed and shown here. This register can be used the for debugging purposes by EEPROM image to perform bug patches and perform services.
Page 382: Virtual Cpu Debug Register (Offset 0X5110)
BCM5722 Programmer’s Guide 10/15/07 CPU D 5110) IRTUAL EBUG EGISTER FFSET Table 325: Virtual CPU Debug Register Fields (Offset 0x5110) Field Description Init Access 31:13 Reserved – 12:10 Irom_St[2:0] The state of the internal ROM image loading FSM Erom_St[3:0] The state of the external EEPROM image loading FSM...
Page 383: Low-Priority Mailboxes
32 bits of these registers, an event (known as a Mailbox Event) is generated to the RX RISC. Only lower 32 bits of these 64-bit low-priority mailbox registers are implemented. Table 328: Low-Priority Mailbox Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only...
Page 384: Interrupt Mailbox 0 Register (Offset 0X5800-0X5807)
BCM5722 Programmer’s Guide 10/15/07 5800–0 5807) NTERRUPT AILBOX EGISTER FFSET “Interrupt Mailbox 0 Register (Offset 0x200–0x207)” on page 238. BD S 5868–0 586F) ECEIVE TANDARD RODUCER NDEX EGISTER FFSET See“Receive BD Standard Producer Ring Index Register (Offset 0x268–0x26F)” on page 239.
Page 385: Flow-Through Queues
Programmer’s Guide BCM5722 10/15/07 HROUGH UEUES Table 330: Flow-Through Queues Registers Offset Registers 0x5C00–0xC403 FTQ Reset Register 0x5C04–0x5CB7 Reserved 0x5CB8–0x5CBB MAC TX FIFO Enqueue Register 0x5CBC–0x5CC7 Reserved 0x5CC8–0x5CCB RXMBUF Cluster Free Enqueue Register (Reserved BCM5906 only) 0x5CCC–0x5CFB Reserved 0x5CFC–0x5CFF RDIQ FTQ Write/Peek Register 0x5D00–0x5FFF...
Page 386: Mac Tx Fifo Enqueue Register (Offset 0X5Cb8)
BCM5722 Programmer’s Guide 10/15/07 Table 331: FTQ Reset Register (Offset 0x5C00) (Cont.) Field Description Init Access Reset Send BD Completion Set this bit to reset the Send BD Completion flow through queue. When set to 0, this flow through queue is ready for use.
Page 387: Table 333: Rxmbuf Cluster Free Enqueue Register (Offset 0X5Cc8)
Programmer’s Guide BCM5722 10/15/07 RXMBUF C 5CC8) LUSTER NQUEUE EGISTER FFSET Note: This register is not applicable to the BCM5906 device. A write to this register frees a cluster of RXMBUFs. The host CPU uses this register to deallocate RXMBUFs after it has processed the received ASF message.
Page 388: Table 335: Functional Truth Table For The Combination Of The Valid, Skip, And Pass Bits
BCM5722 Programmer’s Guide 10/15/07 Table 335 shows the functional truth table for the combination of the Valid, Skip, and Pass bits. Table 335: Functional Truth Table for the Combination of the Valid, Skip, and Pass Bits Valid Skip Pass Scenario Head entry invalid.
Page 389: Table 336: Message Signaled Registers
Programmer’s Guide BCM5722 10/15/07 ESSAGE IGNALED NTERRUPT EGISTERS Table 336: Message Signaled Registers Offset Registers 0x6000–0x6003 MSI Mode Register 0x6004–0x6007 MSI Status Register 0x6008–0x600b MSI FIFO Access Register 0x600C–0x67FF Reserved MSI M 6000) EGISTER FFSET Table 337: MSI Mode Register (Offset 0x6000)
Page 390: Table 339: Msi Fifo Access Register (Offset 0X6008)
BCM5722 Programmer’s Guide 10/15/07 MSI FIFO A 6008) CCESS EGISTER FFSET The MSI FIFO Access Register is used to give an MSI request to the PCI block. The actual MSI data is indicated in the bottom bits. If the MSI is properly enqueued into the FIFO, the overflow bit remains cleared. If the FIFO overflowed, the bit is set and must be written to be cleared.
Page 391: Table 340: General Control Registers-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only
Programmer’s Guide BCM5722 10/15/07 ENERAL ONTROL EGISTERS Table 340: General Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description 0x6800–0x6803 Mode Control Register 0x6804–0x6807 Misc Configuration Register 0x6808–0x680b Misc Local Control Register 0x680c–0x680f Timer Register 0x6810–0x6813 RX-RISC Event Register 0x6814–0x6817...
Page 392: Table 342: Mode Control Register (Offset 0X6800)
BCM5722 Programmer’s Guide 10/15/07 Table 341: General Control Registers—BCM5906 Only (Cont.) Field Description 0x6894–0x6897 Reserved 0x6898–0x689B Chip mode Register 0x689C–0x689F Energy_Det Timer Register 0x68A0–0x68A3 Reserved 0x68A4–0x68A7 Power management Debug Register 0x68A8–0x68AF Reserved 0x68B0–0x68B3 Energy_Det Control Register 0x68B4–0x68ff Reserved 6800) ONTROL...
Page 393 Programmer’s Guide BCM5722 10/15/07 Table 342: Mode Control Register (Offset 0x6800) (Cont.) Field Description Init Access Allow Bad Frames The RX MAC forwards illegal frames to the NIC and marks them as such instead of discarding them. The frames are...
Page 394: Table 343: Miscellaneous Configuration Register (Offset 0X6804)
Wire Speed Enable When this bit is set, wire speed detection is enabled. (BCM5787, BCM5787M, BCM5754, and BCM5754M only) BOND ID 5 (BCM5722, 1 = Super IDDQ Mode Disable BCM5755, BCM5755M, BCM5756M, BCM5757 only) Wire Speed Timer Disable When this bit is set, the wire speed timer is disabled.
Page 395: Table 344: Miscellaneous Local Control Register (Offset 0X6808)
Programmer’s Guide BCM5722 10/15/07 Table 343: Miscellaneous Configuration Register (Offset 0x6804) (Cont.) Field Description Init Access 16:13 Bond ID ID(3:0) 12:8 Reserved – Timer Prescaler Local Core clock frequency in MHz, minus 1, which should 1111111 correspond to each advance of the timer. Reset to all 1.
Page 396: Table 345: Timer Register (Offset 0X680C)
Table 344: Miscellaneous Local Control Register (Offset 0x6808) (Cont.) Field Description Init Access Testclk_25_disable 25-MHz test clock disable (BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757 only) Reserved (other devices) – Gpio_uart_sel GPIO[2:1] pins are shared with UART SDATA_O and SDATA_I pins for the 100-pin FBGA package.
Page 397: Table 346: Rx-Risc Event Register (Offset 0X6810)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only
RISC processor. Note: The version of Rx-RISC Event Register shown in Table 346 applies to BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 only. Table 346: RX-RISC Event Register (Offset 0x6810)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description Init...
Page 398: Table 347: Rx-Risc Event Register (Offset 0X6810)-Bcm5906 Only
BCM5722 Programmer’s Guide 10/15/07 Table 346: RX-RISC Event Register (Offset 0x6810)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only (Cont.) Field Description Init Access Recv List Placement (other Receive list placement FTQ has stalled. devices) SW Event 1 SW Event 1 is set.
Page 399: Table 348: Rx-Risc Timer Reference Register (Offset 0X6814)
Programmer’s Guide BCM5722 10/15/07 RX-RISC T 6814) IMER EFERENCE EGISTER FFSET The Timer Reference register allows the RX-RISC to receive an event when the free-running Timer register counts up to this value. Note: This register is not applicable to the BCM5906 device.
Page 400: Table 350: Serial Eeprom Address Register (Offset 0X6838)
BCM5722 Programmer’s Guide 10/15/07 Table 350: Serial EEPROM Address Register (Offset 0x6838) Field Description Init Access Read/Write If set, the transfer is a read. Complete Set when the transfer is complete. Reset Reset serial EEPROM hardware block. 28:26 Device ID Device ID (A2, A1, A0).
Page 401: Table 353: Mdi Control Register (Offset 0X6844)
Programmer’s Guide BCM5722 10/15/07 Table 352: Serial EEPROM Control Register (Offset 0x6840) (Cont.) Field Description Init Access Clock Output Tri-state Serial EEPROM clock output tristate control MDI C 6844) ONTROL EGISTER FFSET The control register for handling the Management Data Interface, which used to communicate between the physical layer and management layer.
Page 402: Table 354: Rx Cpu Event Enable Register (Offset 0X684C)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only
684C) VENT NABLE EGISTER FFSET Setting a bit in this register enables an interrupt to the CPU or the event. Table 354: RX CPU Event Enable Register (Offset 0x684C)—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description Init Access Flash –...
Page 403: Table 355: Rx Cpu Event Enable Register (Offset 0X684C)-Bcm5906 Only
Programmer’s Guide BCM5722 10/15/07 Table 355: RX CPU Event Enable Register (Offset 0x684C)—BCM5906 Only Field Description Init Access Flash – – Reserved – – HC module – Reserved – EMAC module – Memory Map Enable Bit Set by HW, cleared by SW Reserved - –...
Page 404: Table 356: Wake-On-Lan Registers
BCM5722 Programmer’s Guide 10/15/07 -LAN R EGISTERS Note: The Wake-on-LAN registers do not apply to the BCM5906 device. Table 356: Wake-on-LAN Registers Field Description 0x6880–0x6883 WOL Mode Register 0x6884–0x6887 WOL Config Register 0x6888–0x688B WOL State Machine Status Register 0x688C–0x688F Reserved...
Page 405: Table 359: Wol State Machine Status Register (Offset 0X6888)
Programmer’s Guide BCM5722 10/15/07 Table 358: WOL Config Register (Offset 0x6884) (Cont.) Field Description Init Access 12:11 SD_delay_cfg This is the amount of the delay. • 00 = 0 • 01 = 50 µs • 10 = 150 µs • 11 = 250 µs Power_avail When set to 1, it indicates the main power is available.
Page 406: Table 360: Miscellaneous Cable Sense Control Register (Offset: 0X6890)
6890) ISCELLANEOUS ABLE ENSE ONTROL EGISTER FFSET Table 360: Miscellaneous Cable Sense Control Register (Offset: 0x6890)— BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only Field Description Init Access EEPROM Clock Disable EEPROM Clock Divider fix Divider fix disable This bit is reset by hard_reset...
Page 407: Table 362: Fast Boot Program Counter Register (Offset 0X6894)
Programmer’s Guide BCM5722 10/15/07 Table 361: Miscellaneous Cable Sense Control Register (Offset: 0x6890)—BCM5906 Only (Cont.) Field Description Init Access CLKREQ# Disable CLKREQ# disable This bit is reset by hard_reset. energy_det_sel 1: Select combination of s/w energy_del bit or h/w energy_det debounce signal;...
Page 408: Table 363: Chip Mode Register (Offset: 0X6898)
BCM5722 Programmer’s Guide 10/15/07 Table 362: Fast Boot Program Counter Register (Offset 0x6894) (Cont.) Field Description Init Access 30:0 FastBoot Program This field is used by the CPU to keep track of the location of the phase Counter 1 bootcode in RX MBUF. These bits behave identical to bit 31 in that they have no effect on state machine operation and they are cleared only by a power-on reset.
Page 409: Table 364: Energy Detect Timer Register (Offset: 0X689C)
Programmer’s Guide BCM5722 10/15/07 689C) NERGY ETECT IMER EGISTER FFSET This register is used to debounce the raw energy_det signal from the EPHY core. Note: This register is applicable to BCM5755, BCM5755M, BCM5906, BCM5906M only. In BCM5755 and BCM5755M, this register is used as part of CableSense feature.
Page 410: Table 365: Miscellaneous Clock Control Register (Offset: 0X68A0)
68A0) ISCELLANEOUS LOCK ONTROL EGISTER FFSET This register is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757 devices only. Some of the bits in this register are initialized by hard_reset. Table 365: Miscellaneous Clock Control Register (Offset: 0x68A0) Field Description Reset...
Page 411: Table 366: Power Management Debug Register (Offset: 0X68A4)
Programmer’s Guide BCM5722 10/15/07 Table 365: Miscellaneous Clock Control Register (Offset: 0x68A0) (Cont.) Field Description Reset Init Access Frequency • 1 = Enable frequency multiplier to generate a 62.5- multiplier Enable MHz clock from XTAL clock • 0 = Disable Frequency multiplier This bit should be used together with bit0.
Page 412: Table 367: Energy_Det Control Register (Offset: 0X68B0)
BCM5722 Programmer’s Guide 10/15/07 Table 366: Power Management Debug Register (Offset: 0x68A4) (Cont.) Field Description Reset Init Access PERST Override This bit is used to override the PERSTN so that internal Hard_ CPU can access the PCIe register when Perstn is...
Page 413 Programmer’s Guide BCM5722 10/15/07 Table 367: Energy_Det Control Register (Offset: 0X68B0) (Cont.) Field Description Init Access Debounce_low_ctrl[1:0 00: Debounce engery_det low for another 5 sec 01: Debounce engery_det low for another 10 sec 10: Debounce engery_det low for another 15 sec...
Page 414: Table 368: Asf Support Registers
BCM5722 Programmer’s Guide 10/15/07 ASF S UPPORT EGISTERS Note: ASF Support registers are not applicable to the BCM5906 device. Table 368: ASF Support Registers Field Description 0x6C00–0x6C03 ASF Control register 0x6C04–0x6C07 SMBus Input register 0x6C08–0x6C0b SMBus Output register 0x6C0c–0x6C0f Watchdog Timer 0x6C10–0x6C13...
Page 415: Table 369: Asf Control Register (Offset 0X6C00)
Programmer’s Guide BCM5722 10/15/07 ASF C 6C00) ONTROL EGISTER FFSET Table 369: ASF Control Register (Offset 0x6C00) Field Description Init Access SMB Early Attn When set, the SMB interface sets the ASF_GRC_ATTN bit as soon as slave activity is detected. When cleared, the attention bit is not set until an address match occurs.
Page 416: Table 370: Smbus Input Register (Offset 0X6C04)
Input data from the SMBus interface. Note: The BCM5722 Ethernet controller uses a 5-byte internal input FIFO for SMBus messages that must be cleared if an error is indicated by the SMB Input Status field. This FIFO is cleared by continually reading the SMBus Data In field until the SMBus In Done bit is set, then clearing the SMBus In Done bit by writing a 1.
Page 417: Table 371: Smbus Output Register (Offset 0X6C08)
Programmer’s Guide BCM5722 10/15/07 6C08) UTPUT EGISTER FFSET Table 371: SMBus Output Register (Offset 0x6C08) Field Description Init Access 31:29 Reserved. – SMB Clock Input Value Value on the SMB Clock pin when the SMBus interface is in bit-bang mode.
Page 418: Table 372: Asf Watchdog Timer Register (Offset 0X6C0C)
Outgoing data byte for the SMB transaction. Note: The BCM5722 Ethernet controller uses a 5-byte internal output FIFO for SMBus messages. When an SMBus message is begun by setting the SMB Output Start bit, the software must write the next output byte within 100 µs, or an underflow may occur and invalidate the entire SMBus message.
Page 419: Table 374: Poll Asf Timer Register (Offset 0X6C14)
Programmer’s Guide BCM5722 10/15/07 ASF T 6C14) IMER EGISTER FFSET Table 374: Poll ASF Timer Register (Offset 0x6C14) Field Description Init Access 31:8 Reserved – Poll timer A countdown timer which decrements at the rate of one tick per 5 ms. When the counter reaches a value of zero,...
Page 420: Table 378: Smbus Driver Select Register (Offset 0X6C24)
BCM5722 Programmer’s Guide 10/15/07 6C24) RIVER ELECT EGISTER FFSET Table 378: SMBus Driver Select Register (Offset 0x6C24) Field Description Init Access 31: 1 Reserved – Driver Select Set to 1 to enable SM_DATA_OUT and SM_CLK_OUT to use new SMBus interface.
Page 421: Table 381: Auxiliary Smbus Master Status Register (Offset 0X6C40)
Programmer’s Guide BCM5722 10/15/07 6C40) UXILIARY ASTER TATUS EGISTER FFSET Table 381: Auxiliary SMBus Master Status Register (Offset 0x6C40) Field Description Init Access 31:8 Reserved – CRC/PEC Error • 0 = No CRC/PEC Error detected. • 1 = CRC/PEC Error Detected. This bit is set only by hardware and can be reset by writing a 1 to this position.
Page 422: Table 382: Auxiliary Smbus Master Control Register (Offset 0X6C44)
BCM5722 Programmer’s Guide 10/15/07 UXILIARY ASTER ONTROL EGISTER FFSET Table 382: Auxiliary SMBus Master Control Register (Offset 0x6C44) Field Description Init Access 31:30 Reserved – SMBus Slave Soft Reset Setting this bit will reset the SMBus slave interface. SMBus Softreset •...
Page 423: Table 383: Auxiliary Smbus Master Command Register (Offset 0X6C48)
Programmer’s Guide BCM5722 10/15/07 Table 382: Auxiliary SMBus Master Control Register (Offset 0x6C44) (Cont.) Field Description Init Access Kill • 0 = This will allow the Master Controller interface function to continue normally. • 1 = Stop the current Master transaction in process. This sets the failed status bit and asserts interrupt selected by the SMB interrupt select field.
Page 424: Table 385: Auxiliary Smbus Slave Address/Control Register (Offset 0X6C50)
BCM5722 Programmer’s Guide 10/15/07 6C50) UXILIARY LAVE DDRESS ONTROL EGISTER FFSET Table 385: Auxiliary SMBus Slave Address/Control Register (Offset 0x6C50) Field Description Init Access 31:8 Reserved – SMBus Slave Address Only meaningful if AV flag is set. User also needs to program bit 0 of register 0x6C64 AV_REG to mark address valid based on SMBus 2.0 spec.
Page 425: Table 387: Auxiliary Smbus Slave Data Register (Offset 0X6C58)
Programmer’s Guide BCM5722 10/15/07 6C58) UXILIARY LAVE EGISTER FFSET Table 387: Auxiliary SMBus Slave Data Register (Offset 0x6C58) Field Description Init Access 31:22 Reserved – 21:16 Read Byte Count Indicates the number of bytes read from the FIFO by the Host.
Page 426: Table 389: Smbus Arp Status Register (Offset 0X6C64)
BCM5722 Programmer’s Guide 10/15/07 ARP S 6C64) TATUS EGISTER FFSET Table 389: SMBus ARP Status Register (Offset 0x6C64) Field Description Init Access 31:16 Reserved – 15:14 Reserved – Directed Reset completion • 0 = Has not received a valid Direct Reset command.
Page 427: Table 391: Udid Register 1 (Offset 0X6C6C)
Programmer’s Guide BCM5722 10/15/07 UDID R 1 (O 6C6C) EGISTER FFSET Table 391: UDID Register 1 (Offset 0x6C6C) Field Description Init Access 31:16 Subsystem Vendor ID This field may hold a value derived from any of several resources. Example: As assigned by PCI SIG.
Page 428: Table 394: Non-Volatile Memory Interface Registers
BCM5722 Programmer’s Guide 10/15/07 OLATILE EMORY NTERFACE EGISTERS Table 394: Non-Volatile Memory Interface Registers Address Description 0x7000 NVM Command Register 0x7004 NVM Status Register 0x7008 NVM Write Register 0x700c NVM Address Register 0x7010 NVM Read Register 0x7014 NVM Config 1 Register...
Page 429: Table 395: Nvm Command Register (Offset 0X7000)
Programmer’s Guide BCM5722 10/15/07 NVM C 7000) OMMAND EGISTER FFSET Table 395: NVM Command Register (Offset 0x7000) Field Description Init Access 31:28 Policy Error Reports Address Lockout Policy Error violations. 27:18 Reserved – seeprom Write 1 to this bit to start external EEPROM reset sequence. HW checks the START reset start condition and issues 9 dummy cycles to reset the external EEPROM.
Page 430: Table 397: Nvm Write Register (Offset 0X7008)
0 to 3 control the drive value of the SCK, CS_L, SO, and SI pins respectively. For BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757 in a 144-pin FBGA package, when bitbang_mode is set, bits 0 to 5 control the drive value of the SCL, SDA, SDK, CS_L, SO, and SI pins respectively.
Page 431: Table 400: Nvm Config 1 Register (Offset 0X7014)
Programmer’s Guide BCM5722 10/15/07 NVM C 7014) ONFIG EGISTER FFSET Table 400: NVM Config 1 Register (Offset 0x7014) Field Description Init Access compat_bypass Enable the 5701 legacy SEEPROM interface to bypass this interface. 30:28 PageSize These bits indicate the page size of the attached flash device.
Page 432: Table 401: Nvm Config 2 Register (Offset 0X7018)
BCM5722 Programmer’s Guide 10/15/07 Table 400: NVM Config 1 Register (Offset 0x7014) (Cont.) Field Description Init Access Status Bits This field represents the bit offset in the status command • 0 if flash_mode = response to interpret as the ready flag.
Page 433: Table 402: Nvm Config 3 Register (Offset 0X701C)
Programmer’s Guide BCM5722 10/15/07 NVM C 701C) ONFIG EGISTER FFSET Table 402: NVM Config 3 Register (Offset 0x701C) Field Description Init Access 31:24 read_cmd This is the Flash/SEEPROM read command. • 0xFF if flash_mode = 1 Following this command, any number of bytes may be •...
Page 434: Table 404: Nvm Access Register (Offset 0X7024)
RX RISC CPU. If the RX RISC CPU is executing bootcode and the ARB_WON0 bit is set when the CPU is stopped, the host driver software must also set the REQ_CLR0 bit to release the NVRAM lock held by the bootcode, otherwise, no other software is able to access NVRAM until the BCM5722 Ethernet controller is reset. NVM A...
Page 435: Table 405: Nvm Write1 Register (Offset 0X7028)
Programmer’s Guide BCM5722 10/15/07 NVM W 7028) RITE EGISTER FFSET Table 405: NVM Write1 Register (Offset 0x7028) Field Description Init Access 31:24 Reserved – 23:16 Status Register Data Data written to the status register for the SST25VF512. 15:8 Write Disable Command Flash command to be used when a flash device with a write protect function is used.
Page 436: Table 407: Nvm Auto-Sense Status Register (0X7038H)
BCM5722 Programmer’s Guide 10/15/07 NVM A 7038 ENSE TATUS EGISTER This register is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754 and BCM5754M devices only. Table 407: NVM Auto-Sense Status Register (0x7038h) Field Description Init Access 31:28 Reserved – 27:16 Auto_dec_sel_vec The auto-sense mapping result.
Page 437: Table 408: Bist Registers
Programmer’s Guide BCM5722 10/15/07 BIST R EGISTERS Table 408: BIST Registers Address Description 0x7400 BIST Control Register 0X7404 BIST Status Register 0x7408–0x7BFF Reserved BIST C 7400) ONTROL EGISTER FFSET Table 409: BIST Control Register (Offset 0x7400) Field Description Init Access...
Page 438: Table 411: Bist Status Register (Offset 0X7404)
BCM5722 Programmer’s Guide 10/15/07 BIST S 7404) TATUS EGISTER FFSET This register definition is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5906, and BCM5906M devices only. Table 411: BIST Status Register (Offset 0x7404) Field Description Init Access 31:8 Reserved –...
Page 439 Programmer’s Guide BCM5722 10/15/07 Table 411: BIST Status Register (Offset 0x7404) (Cont.) Field Description Init Access TxMbuf & Misc_BD Status indicating BIST test has failed. BIST Fail TxMbuf & Misc_BD Status indicating BIST has completed when set (TXMBUF). BIST Done RxMbuf BIST Fail Status indicating BIST test has failed.
Page 440: Table 412: Pcie Registers
Programmer’s Guide 10/15/07 EGISTERS Table 412: PCIe Registers Address Description TLP Diagnostic Registers (these are Transaction Layer Protocol Hardware Debug Registers)— BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5754M, BCM5787, BCM5787M only 0x7C00 TLP Control register 0x7C04 TLP Workaround Register 0x7C08 Reserved...
Page 441 Programmer’s Guide BCM5722 10/15/07 Table 412: PCIe Registers (Cont.) Address Description TLP Diagnostic Registers (these are Transaction Layer Protocol Hardware Debug Registers)— BCM5906, BCM5906M only 0x7C00 TLP Control register 0x7C04 TLP Workaround Register 0x7C08:0x7CFF Reserved Data Link Layer Internal Registers...
Page 442: Table 413: Tlp Control Register (Offset 0X7C00)
BCM5722 Programmer’s Guide 10/15/07 Table 412: PCIe Registers (Cont.) Address Description 0x7E20 PHY Receive Error Counter 0x7E24 PHY Receive Framing Error Counter 0x7E28 PHY Receive Error Threshold register 0x7E2C PHY Test Control register 0x7E30 PHY/SerDes Control Override 0x7E34 PHY Timing Parameter Override...
Page 443: Table 414: Transaction Configuration Register (0X7C04)
Programmer’s Guide BCM5722 10/15/07 Table 413: TLP Control Register (Offset 0x7C00) (Cont.) Field Description Init Access Disable UR Error When clear, this bit enables the DMA completion logic to check for a completion packet with an Unsupported Request value. Disable RSV Error When clear, this bit enables the DMA completion logic to check for a completion packet with a Reserved value.
Page 444 BCM5722 Programmer’s Guide 10/15/07 Table 414: Transaction Configuration Register (0x7C04) (Cont.) Field Description Access Reset Init Select Core Clock Override This bit is used by software to allow it to Core access PCIe register when the PCIe PLL can’t lock after power up. This bit when set will select the core clock to drive the PCIe logic.
Page 445 • 000 = 1 • 001 = 2 • 010 = 4 • 011 = 8 • 100 = 16 The BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5754M, BCM5787, and BCM5787M devices can only request a maximum of 1 MSI Message.
Page 446: Table 415: Write Dma Request Upper Address Diagnostic Register (Offset 0X7C10)
BCM5722 Programmer’s Guide 10/15/07 Table 414: Transaction Configuration Register (0x7C04) (Cont.) Field Description Access Reset Init Lom_configuration This bit is when set indicates that the power Core budget for the device is included within the system power budget. Structure. • 0 = Enable (NIC) •...
Page 447: Table 417: Write Dma Length/Byte Enable And Request Diagnostic Register (Offset 0X7C18)
Programmer’s Guide BCM5722 10/15/07 DMA L RITE ENGTH NABLE AND EQUEST IAGNOSTIC EGISTER FFSET 7C18) Note: This register is not applicable to the BCM5906 device. Table 417: Write DMA Length/Byte Enable and Request Diagnostic Register (Offset 0x7C18) Field Description Init...
Page 448: Table 421: Msi Dma Request Upper Address Diagnostic Register (Offset 0X7C28)
BCM5722 Programmer’s Guide 10/15/07 MSI DMA R 7C28) EQUEST PPER DDRESS IAGNOSTIC EGISTER FFSET Note: This register is not applicable to the BCM5906 device. Table 421: MSI DMA Request Upper Address Diagnostic Register (Offset 0x7C28) Field Description Init Access 31:0...
Page 449: Table 424: Slave Request Length And Type Diagnostic Register (Offset 0X7C34)
Programmer’s Guide BCM5722 10/15/07 7C34) LAVE EQUEST ENGTH AND IAGNOSTIC EGISTER FFSET Note: This register is not applicable to the BCM5906 device. Table 424: Slave Request Length and Type Diagnostic Register (Offset 0x7C34) Field Description Init Access 31:26 Reg_slv_len_req Reserved 25:16 –...
Page 450: Table 426: Xmt State Machines And Gated Requests Diagnostic Register (Offset 0X7C3C)
BCM5722 Programmer’s Guide 10/15/07 XMT S 7C3C) TATE ACHINES AND ATED EQUESTS IAGNOSTIC EGISTER FFSET Note: This register is not applicable to the BCM5906 device. Table 426: XMT State Machines and Gated Requests Diagnostic Register (Offset 0x7C3C) Field Description Init...
Page 451: Table 429: Dma Completion Header Diagnostic Register 1 (Offset 0X7C48)
Programmer’s Guide BCM5722 10/15/07 DMA C 1 (O 7C48) OMPLETION EADER IAGNOSTIC EGISTER FFSET Note: This register is not applicable to the BCM5906 device. Table 429: DMA Completion Header Diagnostic Register 1 (Offset 0x7C48) Field Description Init Access 31:0 Reg_hdr0...
Page 452: Table 432: Dma Completion Misc. Diagnostic Register (Offset 0X7C54)
BCM5722 Programmer’s Guide 10/15/07 DMA C 7C54) OMPLETION IAGNOSTIC EGISTER FFSET Note: This register is not applicable to the BCM5906 device. Table 432: DMA Completion Misc. Diagnostic Register (Offset 0x7C54) Field Description Init Access 31:28 Reg_dma_cmpt_misc0 Completion Malform Error Counter 27:24 –...
Page 453: Table 435: Split Controller Misc 0 Register Diagnostic Register (Offset 0X7C60)
Programmer’s Guide BCM5722 10/15/07 7C60) PLIT ONTROLLER EGISTER IAGNOSTIC EGISTER FFSET Note: This register is not applicable to the BCM5906 device. Table 435: Split Controller Misc 0 Register Diagnostic Register (Offset 0x7C60) Field Description Init Access 31:18 Reg_splitctl_misc0 Reserved –...
Page 454: Table 438: Tlp Status Register (Offset 0X7C60)
BCM5722 Programmer’s Guide 10/15/07 TLP D 7C6C) EBUG EGISTER FFSET Note: This register is not applicable to the BCM5906 device. Table 438: TLP Status Register (Offset 0x7C60) Field Description Init Access A4 Device Indication Bit Indicates whether the device is A4 chip...
Page 455 Programmer’s Guide BCM5722 10/15/07 Table 439: Data Link Control Register (Offset 0x7D00) (Cont.) Field Description Init Access Enable Pending Enable this fix to wake up from L1 and flush out pending Completion Packet TLP. Issue Fix CQ10452 • 1 = Disable fix •...
Page 456: Table 440: Data Link Status Register (Offset 0X7D04)
BCM5722 Programmer’s Guide 10/15/07 7D04) TATUS EGISTER FFSET Table 440: Data Link Status Register (Offset 0x7D04) Field Description Init Access 31:26 Reserved Write as 0, ignore when read. 25:23 PHY Link State Current physical layer power state. • 000 = L0 •...
Page 457: Table 441: Data Link Attention Register (Offset 0X7D08)
Programmer’s Guide BCM5722 10/15/07 7D08) TTENTION EGISTER FFSET Table 441: Data Link Attention Register (Offset 0x7D08) Field Description Init Access 31:5 Reserved Write as 0, ignore when read. – Data Link Layer Error Asserted when any of the following bits are set in the data...
Page 458: Table 443: Next Transmit Sequence Number Debug Register (Offset 0X7D10)
BCM5722 Programmer’s Guide 10/15/07 7D10) RANSMIT EQUENCE UMBER EBUG EGISTER FFSET Table 443: Next Transmit Sequence Number Debug Register (Offset 0x7D10) Field Description Init Access 31:12 Reserved Write as 0, ignore when read. 11:0 Next Transmit Transmit sequence number for the next TLP to be sent. 0x000...
Page 459: Table 448: Data Link Ack Timeout Register (Offset 0X7D24)
Programmer’s Guide BCM5722 10/15/07 ACK T 7D24) IMEOUT EGISTER FFSET Table 448: Data Link ACK Timeout Register (Offset 0x7D24) Field Description Init Access 31:11 Reserved Write as 0, ignore when read. 10:0 ACK Latency Timeout ACK latency timeout value in data link layer clock cycles...
Page 460: Table 452: Retry Buffer Purged Pointer Debug Register (Offset 0X7D34)
BCM5722 Programmer’s Guide 10/15/07 7D34) ETRY UFFER URGED OINTER EBUG EGISTER FFSET Table 452: Retry Buffer Purged Pointer Debug Register (Offset 0x7D34) Field Description Init Access 31:11 Reserved Write as 0, ignore when read. 10:0 Retry Buffer Purged Starting address of next TLP to be purged from retry Pointer buffer RAM.
Page 461: Table 456: Dllp Error Counter (Offset 0X7D44)
Programmer’s Guide BCM5722 10/15/07 DLLP E 7D44) RROR OUNTER FFSET Table 456: DLLP Error Counter (Offset 0x7D44) Field Description Init Access 31:16 Reserved Write as 0, ignore when read. 15:0 DLLP Error Counter Counts number of bad DLLPs received (includes bad RO/CR LCRC or bad length) since last read.
Page 462: Table 459: Packet Bist Register (Offset 0X7D50)
BCM5722 Programmer’s Guide 10/15/07 Table 458: Data Link Test Register (Offset 0x7D4C) (Cont.) Field Description Init Access Invert CRC Force entire LCRC to be inverted. Send Bad CRC Force last bit of LCRC to be inverted. BIST R 7D50) ACKET...
Page 463: Table 460: Link Pcie 1.1 Control Register (0X7D54)
Programmer’s Guide BCM5722 10/15/07 1.1 C 7D54) ONTROL EGISTER Table 460: Link PCIe 1.1 Control Register (0x7D54) Field Description Init Reset Access 31:29 Rtbf_ct[2:0] Timing debug control pins for the retry buffer, Chip normally 0. These bits are only writable when...
Page 464: Table 461: Phy Mode Register (Offset 0X7E00)
BCM5722 Programmer’s Guide 10/15/07 Table 460: Link PCIe 1.1 Control Register (0x7D54) (Cont.) Field Description Init Reset Access dASPM10usTimer Disable ASPM 10us Timer before next ASPM Chip L1 request after naked ASPM L1 request. This (hard + is a PCIe1.1 requirement. Assertion of disable soft) will go back to 1.0a version.
Page 465: Table 463: Phy/Link Ltssm Control Register (Offset 0X7E08)
Programmer’s Guide BCM5722 10/15/07 PHY/L LTSSM C 7E08) ONTROL EGISTER FFSET Table 463: PHY/Link LTSSM Control Register (Offset 0x7E08) Field Description Init Access 31:8 Reserved – DisableScramble Disable scrambling and de-scrambling. DetectState High layer directs LTSSM to detect state if set. The bit is cleared when LTSSM entered into detect state.
Page 466: Table 466: Phy/Link Training N_Fts (Offset 0X7E14)
BCM5722 Programmer’s Guide 10/15/07 PHY/L N_FTS (O 7E14) RAINING FFSET Table 466: PHY/Link Training N_FTS (Offset 0x7E14) Field Description Init Access 31:16 Reserved – Increase_TX_L0s_exit Add programmable register to increase tx L0s exit (BCM5906 only) latency. This may be used to offset the extended tx idle/ active time in the LP version of the SerDes Analog.
Page 467: Table 468: Phy Attention Mask Register (Offset 0X7E1C)
Programmer’s Guide BCM5722 10/15/07 PHY A 7E1C) TTENTION EGISTER FFSET Table 468: PHY Attention Mask Register (Offset 0x7E1C) Field Description Init Access 31:8 Reserved – Hot reset mask Hot reset event mask bit. Link down mask Link down event mask bit.
Page 468: Table 471: Phy Receive Error Threshold Register (Offset 0X7E28)
Receive frame error threshold. When the frame 0x4 (For BCM5787, BCM5787M, Threshold error count exceeds this threshold. The frame BCM5754, and BCM5754M only) error attention bit is set. Threshold=2^n, where 0xF (For BCM5722, BCM5755, n=bits(11:8). BCM5755M, BCM5756M, BCM5757 only) Disparity Error Receive 8b10b running disparity error...
Page 469 Reserved (other devices) Enable Immediate L1 Enable the immediate L1 Exit Fix Exit Issue Fix (CQ9901 • 0 = Disable Fix Fix) (BCM5722, • 1 = Enable Fix BCM5755, BCM5755M, Note: Refer to E1_5751B0_09901 in the 5751-ES4xx-R BCM5756M, BCM5757 Errata for details.
Page 470: Table 473: Phy/Serdes Control Override Register (Offset 0X7E30)
BCM5722 Programmer’s Guide 10/15/07 Table 472: PHY Test Control Register (Offset 0x7E2C) (Cont.) Field Description Init Access Fast Symbol Lock Up When this bit is: • Set to 1, the symbol boundary locks after receiving the first COM symbol. • Clear, the symbol boundary locks after receiving four COM symbols within a 64-symbol time.
Page 471: Table 474: Phy Timing Parameter Override Register (Offset 0X7E34)
Programmer’s Guide BCM5722 10/15/07 PHY T 7E34) IMING ARAMETER VERRIDE EGISTER FFSET Table 474: PHY Timing Parameter Override Register (Offset 0x7E34) Field Description Init Access ts1NumOverride Set to override the TS1 number to be sen out in polling active state with the value in bit (27:16) of this register from the specification defined value.
Page 472: Table 476: Phy Hardware Diagnostic 2 Register (Offset 0X7E3C)
BCM5722 Programmer’s Guide 10/15/07 PHY H 7E3C) ARDWARE IAGNOSTIC EGISTER FFSET Table 476: PHY Hardware Diagnostic 2 Register (Offset 0x7E3C) Field Description Init Access 31:0 LTSSM State Machine LTSSM state machine states: State • 31:28 = Main State. • 27:26 = Detect substate.
Page 473: Table 477: Transceiver Register Map
Programmer’s Guide BCM5722 10/15/07 RANSCEIVER EGISTERS This section describes the MII registers of the integrated 10/100/1000T PHY transceivers. The access to the transceiver registers is provided indirectly through the MII Communication Register (see “MI Communication Register (Offset 0x44C)” on page 251) of the MAC.
Page 474: Table 478: Mii Control Register (Phy_Addr = 0X1, Reg_Addr = 00H)
• 1 = PHY reset • 0 = Normal operation Internal Loopback The BCM5722 Ethernet controller can be placed into internal loopback mode by writing a 1 to bit 14 of the MII Control Register. The loopback mode can be cleared by writing a 0 to bit 14 of the MII Control Register, or by resetting the chip.
Page 475: Table 479: Mii Status Register (Phy_Addr = 0X1, Reg_Addr = 01H)
8 of the Control Register. Setting this bit to a 1 forces the BCM5722 Ethernet controller into full-duplex operation, and setting this bit to a 0 forces the BCM5722 Ethernet controller into half-duplex operation. • 1 = Full-duplex •...
Page 476 • 1 = Preamble can be suppressed • 0 = Preamble always required Auto-negotiation The BCM5722 Ethernet controller returns a 1 on bit 15 of Complete the Auxiliary Status Summary Register (see “Auxiliary Status Summary Register (PHY_Addr = 0x1, Reg_Addr = 19h)”...
Page 477: Table 480: Phy Identifier Registers (Phy_Addr = 0X1, Reg_Address 02H)
Init Access Link Status The BCM5722 Ethernet controller returns a 1 on bit 2 of the MII Status Register when the link monitor is in the Link Pass state, indicating that a valid link has been established. Otherwise, it returns a 0. When a link failure...
Page 478: Table 482: Auto-Negotiation Advertisement Register (Phy_Addr = 0X1, Reg_Addr = 04H)
Next Page exchange. When this bit is written to 0, Next Page exchange is controlled automatically by the BCM5722 Ethernet controller. When this bit is 0 and the BCM5722 Ethernet controller is advertising no 1000BASE-T capability, no exchange of Next Pages occurs.
Page 479 Bits 4:0 of the auto-negotiation advertisement register 00001 indicate the protocol type. The value 00001 indicates that the BCM5722 Ethernet controller belongs to the 802.3 class of PHY transceivers. 00001 indicates IEEE 802.3 CSMA/CD Bro adco m Co rp or atio n...
Page 480: Table 483: Auto-Negotiation Link Partner Ability Register (Phy_Addr = 0X1, Reg_Addr = 05H)
Description Init Access Next Page The BCM5722 Ethernet controller returns a 1 on bit 15 of the Link Partner Ability register when the link partner wishes to transmit Next Page information. • 1 = Link partner has Next Page ability •...
Page 481: Table 484: Auto-Negotiation Expansion Register (Phy_Addr = 0X1, Reg_Addr = 06H)
Description Init Access 10BASE-T Full-Duplex The BCM5722 Ethernet controller returns a 1 on bit 6 of the Link Partner Capability Ability register when the link partner has advertised 10BASE-T full-duplex capability, otherwise, it returns a 0. • 1 = Link partner is 10BASE-T full-duplex capable •...
Page 482: Table 485: Next Page Transmit Register (Phy_Addr = 0X1, Reg_Addr = 07H)
• 0 = Unformatted page. Acknowledge2 When this bit is set to 1, the BCM5722 Ethernet controller indicates that it can comply with the Next Page request. When this bit is set to 0, the BCM5722 Ethernet controller indicates that it cannot comply with the Next Page request.
Page 483: Table 486: Link Partner Received Next Page Register (Phy_Addr = 0X1, Reg_Addr = 08H)
• 0 = Cannot comply with message. Toggle The link partner toggles this bit between different Next Page exchanges to insure a functional synchronization to the BCM5722 Ethernet controller. Toggles between exchanges of different Next Pages. 10:0 Message Code Field These 11 bits make up the message code defined IEEE 0...0...
Page 484: Table 487: 1000Base-T Control Register (Phy_Addr = 0X1, Reg_Addr = 09H)
When bit 11 is set to 1, the BCM5722 Ethernet controller is configured as master. When bit 11 is set to 0, the BCM5722 Ethernet controller is configured as slave. When read, this bit returns the last value written.
Page 485: Table 488: 1000Base-T Status Register (Phy_Addr = 0X1, Reg_Addr = 0Ah)
• 1 = Local transmitter is Master. • 0 = Local transmitter is Slave. Local Receiver Status The BCM5722 Ethernet controller returns a 1 on bit 13 of the 1000BASE-T Status Register when the local receiver status is OK, otherwise, it returns a 0.
Page 486: Table 489: Ieee Extended Status Register (Phy_Addr = 0X1, Reg_Addr = 0Fh)
Field Description Init Access Remote Receiver The BCM5722 Ethernet controller returns a 1 on bit 12 of the Status 1000BASE-T Status Register when the remote receiver status is OK, otherwise, it returns a 0. • 1 = Remote receiver OK.
Page 487: Table 490: Phy Extended Control Register (Phy_Addr = 0X1, Reg_Addr = 10H)
The automatic MDI crossover function can be disabled by Crossover writing a 1 to bit 14 of the PHY Extended Control Register. When the bit is written to 0, the BCM5722 Ethernet controller performs the automatic MDI crossover function (see “Automatic MDI Crossover”...
Page 488 When bit 3 of the PHY Extended Control Register is written to 1, the BCM5722 Ethernet controller forces all LEDs into the OFF state. When bit 3 is written to 0, the BCM5722 Ethernet controller resets all LEDs to normal operation.
Page 489: Table 491: Phy Extended Status Register (Phy_Addr = 0X1, Reg_Addr = 11H)
• 1 = Remote receiver OK. • 0 = Remote receiver not OK since last read. Local Receiver Status The BCM5722 Ethernet controller returns a 1 on bit 10 of the PHY Extended Status Register when the local receiver status is OK.
Page 490 • 1 = Bad ESD error detected since last read. • 0 = No bad ESD error since last read. Receive Error Detected The BCM5722 Ethernet controller returns a 1 on bit 3 of the PHY Extended Status Register if a packet was received with an invalid code since the last time this register was read, otherwise, it returns a 0.
Page 491: Table 492: Receive Error Counter (Phy_Addr = 0X1, Reg_Addr = 12H)
S3MII Error Counter increments each time the BCM5722 Ethernet controller detects a S3MII overrun/underrun event. False Carrier Sense Counter increments each time the BCM5722 Ethernet controller detects a false carrier on the receive input. These counters freeze at the maximum value FFh. The counters automatically clear when read.
Page 492: Table 494: Receiver Not_Ok Counters (Phy_Addr = 0X1, Reg_Addr = 14H, Normal Operation)
1 (PHY_Addr = 0X1, REG_Addr = 1EH)” on page 480) is clear). Remote Receiver Number of times the BCM5722 Ethernet controller NOT_OK Counter detected that the remote receiver was not OK since last read (when PHY Test Register 1. CRC_Error_Count_Visibility bit (see “PHY Test Register...
Page 493: Table 496: Expansion Register Access Register (Phy_Addr = 0X1, Reg_Addr = 17H)
Programmer’s Guide BCM5722 10/15/07 (PHY_ADDR = 0 1, R = 17 XPANSION EGISTER CCESS EGISTER When enabled, this register serves as an index to the expansion registers. The value of the expansion register can be read/ written through register 15h (see “Expansion Register Access Data (PHY_ADDR = 01h, REG_ADDR = 15h)”...
Page 494: Table 498: Expansion Register 00H: Receive/Transmit Packet Counter
BCM5722 Programmer’s Guide 10/15/07 XPANSION EGISTER ECEIVE RANSMIT ACKET OUNTER The following expansion registers are enabled by writing to “Expansion Register Access Register (PHY_ADDR = 0x1, Reg_Addr = 17h)” on page 434 bits [11:0] = F00h, and read/write access is through register 15h.
Page 495: Table 500: Expansion Register 03H: Serdes Control
Programmer’s Guide BCM5722 10/15/07 Expansion Interrupt Status These bits corresponds to the Expansion Interrupt Status bits. Transmit CRC Error (Copper Only) Bit 0 = 1 indicates that a transmit CRC error occurred since the register was last read, otherwise, it returns a 0.
Page 496: Table 501: Expansion Register 04H: Multicolor Led Selector
BCM5722 Programmer’s Guide 10/15/07 LED S XPANSION EGISTER ULTICOLOR ELECTOR The following expansion registers are enabled by writing to “Expansion Register Access Register (PHY_ADDR = 0x1, Reg_Addr = 17h)” on page 434 bits [11:0] = F04h, and read/write access is through register 15h.
Page 497: Table 502: Expansion Register 05H: Multicolor Led Flash Rate Controls
Programmer’s Guide BCM5722 10/15/07 In Phase When both MULTICOLOR[2:1] are set to the same mode, the outputs of MULTICOLOR[1] and MULTICOLOR[2] both toggle at the same time. This bit determines whether the LEDs are identical to each other or inverse from each other. When the two LED pins are attached to a special multicolored LED, the resulting LED color alternates between Off/Amber (In Phase) or Red/Green (Out of Phase).
Page 498: Table 503: Expansion Register 06H: Multicolor Led Programmable Blink Controls
BCM5722 Programmer’s Guide 10/15/07 Alternation Rate Setting bits [11:6] changes the width and gap of the alternating LED modes. These bits are only valid when the MULTICOLOR[1] Multicolor Selector and or the MULTICOLOR[2] Multicolor Selector bits = 0110. LED's duty cycle is exactly 50%.
Page 499: Table 504: Expansion Register 10H: Cable Diagnostic Controls
Programmer’s Guide BCM5722 10/15/07 XPANSION EGISTER ABLE IAGNOSTIC ONTROLS The following expansion registers are enabled by writing to “Expansion Register Access Register (PHY_ADDR = 0x1, Reg_Addr = 17h)” on page 434 bits [11:0] = F10h, and read/write access is through register 15h.
Page 500: Table 505: Expansion Register 11H: Cable Diagnostic Results
BCM5722 Programmer’s Guide 10/15/07 XPANSION EGISTER ABLE IAGNOSTIC ESULTS The following Expansion registers are enabled by writing to “Expansion Register Access Register (PHY_ADDR = 0x1, Reg_Addr = 17h)” on page 434 bits [11:0] = F11h, and read/write access is through register 15h.
Page 501: Table 506: Expansion Register 12H: Cable Diagnostic Lengths Channels1/2
Channel 2 Length When the BCM5722 Ethernet controller detects an open or short on the cable, bits [15:8] reflect how far away the open or short is from the BCM5722 Ethernet controller. When no open or short is detected, bits [15:8] reflect the cable length connected to channel 2 in meters.
Page 502: Table 507: Expansion Register 13H: Cable Diagnostic Lengths Channels 3/4
Channel 4 Length When the BCM5722 Ethernet controller detects an open or short on the cable, bits [15:8] reflect how far away the open or short is from the BCM5722 Ethernet controller. When no open or short is detected, bits [15:8] reflect the cable length connected to channel 2 in meters.
Page 503: Table 508: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 000, Normal)
Length BCM5722 Ethernet controller receives packets up to 25 KB in length. When the bit is written to 0, the BCM5722 Ethernet controller only receives packets up to 4.5 KB in length. • 1 = Allow reception of extended length packets.
Page 504 Diagnostic Mode When bit 3 of the Auxiliary Control Register is written to 1, the BCM5722 Ethernet controller enters a special mode to diagnose faults within the cable plant. See Application Notes for details. • 1 = Cable diagnostic mode enabled.
Page 505: Table 509: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 001, 10Base-T)
Programmer’s Guide BCM5722 10/15/07 (PHY_A 1, R = 18 = 001, UXILIARY ONTROL EGISTER HADOW 10BASE-T) Table 509: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 001, 10BASE-T) Field Description Init Access Manchester Code Error Indicates that a Manchester code violation was received.
Page 506: Power Control)
BCM5722 Programmer’s Guide 10/15/07 Table 509: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 001, 10BASE-T) (Cont.) Field Description Init Access SQE Enable Mode Writing a 1 to this bit enables SQE mode. Writing a 0 disables it.This bit is valid only during 10BASE-T operation.
Page 507: Table 511: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 100, Misc Test 1)
Programmer’s Guide BCM5722 10/15/07 (PHY_A 1, R = 18 = 100, UXILIARY ONTROL EGISTER HADOW Table 511: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 100, Misc Test 1) Field Description Init Access Lineside [Remote] Setting bit 15 enables lineside [remote] loopback of the...
Page 508: Table 512: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 111, Misc Control)
BCM5722 Programmer’s Guide 10/15/07 (PHY_A 1, R = 18 = 111, UXILIARY ONTROL EGISTER HADOW ONTROL Table 512: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 111, Misc Control) Field Description Init Access Write Enable (Bits 11:3) • 1 = Write bits 14:0.
Page 509: Table 513: Auxiliary Status Summary Register (Phy_Addr = 0X1, Reg_Addr = 19H)
Field Description Init Access Auto-negotiation The BCM5722 Ethernet controller returns a 1 on bit 15 of the Complete Auxiliary Status Summary Register when auto-negotiation is complete. This bit returns a 0 while auto-negotiation is in progress. • 1 = Auto-negotiation complete.
Page 510 • 0 = Parallel link fault not detected. Remote Fault The BCM5722 Ethernet controller returns a one on bit 6 of the Auxiliary Status Summary Register when the link partner has advertised detection of a remote fault, otherwise, it returns a •...
Page 511 Init Access Link Status The BCM5722 Ethernet controller returns a 1 on bit 2 of the auxiliary status summary register when the link status is good, otherwise, it returns a 0. • 1 = Link is up (Link Pass state).
Page 512: Table 514: Interrupt Status Register (Phy_Addr = 0X1, Reg_Addr = 1Ah)
• 0 = Interrupt cleared. HCD No Link Bit 9 of the Interrupt Status Register is set to 1 by the BCM5722 Ethernet controller when the negotiated HCD was not able to establish a link. The bit is cleared when the register is read.
Page 513 • 1 = Local receiver status changed since last read. • 0 = Interrupt cleared. Duplex Mode Change The BCM5722 Ethernet controller returns a one on bit 3 of the Interrupt Status Register when the duplex mode has changed since the last time this register was read, otherwise, it returns a 0.
Page 514: Table 515: Interrupt Mask Register (Phy_Addr = 0X1, Reg_Addr = 1Bh)
BCM5722 Programmer’s Guide 10/15/07 (PHY_A 1, R = 1B NTERRUPT EGISTER Table 515: Interrupt Mask Register (PHY_Addr = 0x1, Reg_Addr = 1Bh) Field Description Init Access 15:0 Interrupt Mask Vector When bit n of the Interrupt Mask Register is written to 1, the 11…1...
Page 515: Table 517: Clock Alignment Control Register (Address 1Ch, Shadow Value 00011)
Programmer’s Guide BCM5722 10/15/07 (PHY_A 1, R = 1C 00011 LOCK LIGNMENT ONTROL HADOW Table 517: Clock Alignment Control Register (Address 1Ch, Shadow Value 00011) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 516: Table 518: Spare Control 2 Register (Address 1Ch, Shadow Value 00100)
BCM5722 Programmer’s Guide 10/15/07 2 (PHY_A 1, R = 1C 00100 PARE ONTROL HADOW Table 518: Spare Control 2 Register (Address 1Ch, Shadow Value 00100) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 517: Table 519: Spare Control 3 Register (Address 1Ch, Shadow Value 00101)
Programmer’s Guide BCM5722 10/15/07 3 (PHY_A 1, R = 1C 00101 PARE ONTROL HADOW Table 519: Spare Control 3 Register (Address 1Ch, Shadow Value 00101) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 518: Table 520: Led Status Register (Address 1Ch, Shadow Value 01000)
BCM5722 Programmer’s Guide 10/15/07 LED S (PHY_A 1, R = 1C 01000 TATUS HADOW Table 520: LED Status Register (Address 1Ch, Shadow Value 01000) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 519 Programmer’s Guide BCM5722 10/15/07 INTR Indicator When LED Status register bit 6 returns a 0, the device is in the interrupted mode. When this bit returns a 1, the device is not in the interrupted mode. LINKSPD Indicator When LED Status register bits 4:3 return a 00, the device is in the 1000BASE-TX link mode. When these bits return a 01, the device is in the 100BASE-TX link mode.
Page 520: Table 521: Led Control Register (Address 1Ch, Shadow Value 01001)
BCM5722 Programmer’s Guide 10/15/07 LED C (PHY_A 1, R = 1C 01001 ONTROL HADOW Table 521: LED Control Register (Address 1Ch, Shadow Value 01001) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 521: Table 522: Auto Power Down Register (Address 1Ch, Shadow Value 01010)
Programmer’s Guide BCM5722 10/15/07 Link Utilization LED Selector These bits apply to the LED programmed to the ACTIVITY mode only. In the activity LED mode, the LED expresses an estimated activity in terms of blink rate. The blink rate of the LED increases as the activity duty cycle increases by increments of 10%.
Page 522: Table 523: Led Selector 1 Register (Address 1Ch, Shadow Value 01101)
BCM5722 Programmer’s Guide 10/15/07 Wakeup Timer Select The port continues wakeup mode for a time based on the count stored in this register. The minimum value is 84 ms and the maximum value is 1.26s. This only applies when the part is in Auto Power-Down mode.
Page 523 Programmer’s Guide BCM5722 10/15/07 Write Enable During a write to this register, setting LED Selector 1 register bit 15 to a 1 allows writing to bits [7:0] of this register. For reading the values of bits [9:0], perform an MDIO write with bit 15 set to a 0 and preferred shadow values in bits [14:10]. The next MDIO read of register address 1Ch contains the preferred Shadow register values in bits [9:0].
Page 524: Table 524: Led Selector 2 Register (Address 1Ch, Shadow Value 01110)
BCM5722 Programmer’s Guide 10/15/07 LED S 2 (PHY_A 1, R = 1C 01110 ELECTOR HADOW Table 524: LED Selector 2 Register (Address 1Ch, Shadow Value 01110) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 525: Table 525: Led Gpio Control/Status Register (Address 1Ch, Shadow Value 01111)
Programmer’s Guide BCM5722 10/15/07 Shadow Register Selector Bits [14:10] of this register must be set to 01110 to enable read/write to the LED Selector register 2 address 1Ch. LED4 Selector Bits [7:4] of MII register 1Ch with shadow value 01110 select the LED2 output mode.
Page 526: Table 526: Autodetect Sgmii/Media Converter Register (Address 1Ch, Shadow Value 11000)
BCM5722 Programmer’s Guide 10/15/07 Programmable LED I/O Control Setting LED GPIO Control/Status register bits [3:0] set the LED pin to disable LED output. Clearing LED GPIO Control/Status register bits [3:0] set the LED pin to enable LED output. SGMII/M (PHY_A...
Page 527: Table 527: 1000Base-X Auto-Negotiation Debug Register (Address 1Ch, Shadow Value 11010)
Programmer’s Guide BCM5722 10/15/07 1000BASE-X A (PHY_A 1, R = 1C EGOTIATION EBUG HADOW 11010 Table 527: 1000BASE-X Auto-Negotiation Debug Register (Address 1Ch, Shadow Value 11010) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 528 BCM5722 Programmer’s Guide 10/15/07 Comma Detected Bit 7 of 1000BASE-X Auto-negotiation Debug register indicates a comma was detected since last read. AN_Sync_Status Bit 6 of 1000BASE-X Auto-negotiation Debug register indicates the AN_sync_status has not failed since last read. Idle Detect State Bit 5 of 1000BASE-X Auto-negotiation Debug register indicates the idle detect state entered since last read.
Page 529: Table 528: Auxiliary 1000Base-X Control Register (Address 1Ch, Shadow Value 11011)
Programmer’s Guide BCM5722 10/15/07 1000BASE-X C (PHY_A 1, R = 1C UXILIARY ONTROL HADOW 11011 Table 528: Auxiliary 1000BASE-X Control Register (Address 1Ch, Shadow Value 11011) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 530: Table 529: Auxiliary 1000Base-X Status Register (Address 1Ch, Shadow Value 11100)
In this mode, the BCM5722 Ethernet controller can transmit packets up to 9 KB in length. When this bit is cleared, the FIFO elasticity is set to low latency. In this mode, the BCM5722 Ethernet controller can transmit packets up to 4.5 KB in length.
Page 531 Programmer’s Guide BCM5722 10/15/07 Shadow Register Selector Bits [14:10] of this register must be set to 11100 to enable read/write to the Auxiliary 1000BASE-X Status register Link Status Change Bit 9 of Auxiliary 1000BASE-X Status register indicates that the link status has changed since the last register read.
Page 532: Table 530: Misc 1000Base-X Status Register (Address 1Ch, Shadow Value 11101)
BCM5722 Programmer’s Guide 10/15/07 1000BASE-X S (PHY_A 1, R = 1C 11101 TATUS HADOW Table 530: Misc 1000BASE-X Status Register (Address 1Ch, Shadow Value 11101) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 533 Programmer’s Guide BCM5722 10/15/07 False Carrier Detected Bit 5 of Misc 1000BASE-X Status register indicates a false carrier detected since the last read. CRC Error Detected Bit 4 of Misc 1000BASE-X Status register indicates a CRC error detected since the last read.
Page 534: Table 531: Autodetect Medium Register (Address 1Ch, Shadow Value 11110)
BCM5722 Programmer’s Guide 10/15/07 (PHY_A 1, R = 1C 11110 UTODETECT EDIUM HADOW Table 531: Autodetect Medium Register (Address 1Ch, Shadow Value 11110) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 535 Programmer’s Guide BCM5722 10/15/07 SerDes Auto Power Down mode Bit 4 of the Autodetect Medium register enables the power down of SerDes when the filtered signal detect is inactive. Power Down Inactive Interface Bit 3 of the Autodetect Medium register enables the power down of SerDes when copper is selected, and power down of copper when SerDes is selected.
Page 536: Table 532: Mode Control Register (Address 1Ch, Shadow Value 11111)
BCM5722 Programmer’s Guide 10/15/07 (PHY_A 1, R = 1C 11111 ONTROL HADOW Table 532: Mode Control Register (Address 1Ch, Shadow Value 11111) Field Description Init Access Write Enable • 1 = Write bits [9:0]. • 0 = Read bits [9:0].
Page 537 Programmer’s Guide BCM5722 10/15/07 SerDes link Bit 6 of the Mode Control register indicates the link status of the SerDes interface is up. Otherwise, it reads a 0. Copper Energy Detect Bit 5 of the Mode Control register indicates that energy is detected in the copper interface. Otherwise, it reads a 0.
Page 538: Table 533: Hcd Status Register (Phy_Addr = 0X1, Reg_Addr = 1Dh, Bit 15 = 1)
BCM5722 Programmer’s Guide 10/15/07 HCD S (PHY_A 1, R = 1D 15 = 1) TATUS EGISTER Table 533: HCD Status Register (PHY_Addr = 0x1, Reg_Addr = 1Dh, Bit 15 = 1) Field Description Init Access Enable Shadow • 1 = Select Shadow register.
Page 539: Table 534: Master/Slave Seed Register (Phy_Addr = 0X1, Reg_Addr = 1Dh, Bit 15 = 0)
Programmer’s Guide BCM5722 10/15/07 (PHY_A 1, R = 1D 15 = 0) ASTER LAVE EGISTER Table 534: Master/Slave Seed Register (PHY_Addr = 0x1, Reg_Addr = 1Dh, Bit 15 = 0) Field Description Init Access Enable Shadow • 1 = Select Shadow register.
Page 540: Table 536: Mii Management Frame Format
BCM5722 Programmer’s Guide 10/15/07 (BCM5906/BCM5906M) RANSCEIVER EGISTERS This section describes the MII registers of the integrated 10/100 PHY transceivers. The access to the transceiver registers is provided indirectly through the MII Communication Register (see “MI Communication Register (Offset 0x44C)” on page 251) of the MAC.
Page 541: Table 537: Mii Register Summary
Programmer’s Guide BCM5722 10/15/07 To put a transceiver with PHY address 00001 into loopback mode, the following MII write instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0101 00001 00000 10 0100 0000 0000 0000 1...
Page 542 008Ah 28(1Ch) 10Base-T Auxiliary Error and General Status 002Xh Register 29(1Dh) Auxiliary Mode Register X004h 30(1Eh) Auxiliary Multi PHY Register 0000h 31(1Fh) Broadcom Test Register 000Bh 16(10h) Miscellaneous Control Register 0000h 17(11h) Reserved 0000h 18(12h) Reserved 0000h 19(13h) Cable Diagnostic Register...
Page 543: Table 538: Control Register (Address 00D, 00H)
Programmer’s Guide BCM5722 10/15/07 MII R EGISTER ETAILED ESCRIPTION The following tables describe individual register bits and their function. MII Control Register Table 538: Control Register (Address 00d, 00h) Name Description Default Soft Reset 1 = PHY reset (SC) 0 = Normal operation...
Page 544 BCM5722 Programmer’s Guide 10/15/07 Auto-Negotiation Enable Auto-negotiation can be disabled either by hardware or software control. If the ANEN input pin is driven to logic 0, auto- negotiation is disabled by hardware control. If bit 12 of the Control Register is written with a value of 0, auto-negotiation is disabled by software control.
Page 545: Table 539: Mii Status Register (Address 01D, 01H)
Programmer’s Guide BCM5722 10/15/07 MII Status Register Table 539: MII Status Register (Address 01d, 01h) Name Description Default 100BASE-T4 Capability 0 = Not 100BASE-T4 capable 100BASE-TX FDX Capability 1 = 100BASE-TX full-duplex capable 100BASE-TX Capability 1 = 100BASE-TX half-duplex capable...
Page 546: Table 540: Phy Identifier Registers (Addresses 02D And 03D, 02H And 03H)
PHYID LOW 6xxxh Broadcom Corporation has been issued an Organizationally Unique Identifier (OUI) by the IEEE. It is a 24-bit number (00- 0A–F7) expressed as hexadecimal values. This 24 bit OUI number is represented in binary as OUI[1:24] = 00000000 01010000 11101111.
Page 547: Table 541: Auto-Negotiation Advertisement Register (Address 04D, 04H)
Programmer’s Guide BCM5722 10/15/07 Auto-Negotiation Advertisement Register Table 541: Auto-Negotiation Advertisement Register (Address 04d, 04h) Name Description Default Next Page 1 = Next page ability is enabled 0 = Next page ability is disabled Reserved – – Remote Fault 1 = Transmit remote fault...
Page 548: Table 542: Auto-Negotiation Link Partner Ability Register (Address 05D, 05H)
BCM5722 Programmer’s Guide 10/15/07 Resetting the chip restores the default bit values. Reading the register returns the values last written to the corresponding bits, or else the default values if no write has been completed since the last chip reset.
Page 549: Table 543: Auto-Negotiation Expansion Register (Address 06D, 06H)
Programmer’s Guide BCM5722 10/15/07 LP Advertise Bits Bits 9:5 of the Link Partner Ability register reflect the abilities of the link partner. A 1 on any of these bits indicates that the link partner is capable of performing the corresponding mode of operation. Bits 9:5 are cleared any time auto-negotiation is restarted or the PHY is reset.
Page 550: Table 544: Next Page Transmit Register (Address 07D, 07H)
BCM5722 Programmer’s Guide 10/15/07 Link Partner Auto-Negotiation Able Bit 0 of the Auto-Negotiation Expansion Register returns a 1 when the link partner is known to have auto-negotiation capability. Before any auto-negotiation information is exchanged, or if the link partner does not comply with IEEE auto- negotiation, the bit returns a value of 0.
Page 551: Table 545: Next Page Transmit Register (Address 08D, 08H)
Programmer’s Guide BCM5722 10/15/07 Auto-negotiation Link Partner (LP) Next Page Transmit Register Table 545: Next Page Transmit Register (Address 08d, 08h) Name Description Default Next Page 1 = Additional next page(s) follows 0 = Last page Reserved Message Page 1 = Message page 0 = Unformatted page...
Page 552: Table 546: 100-Base-X Auxiliary Control Register (Address 16D, 10H)
BCM5722 Programmer’s Guide 10/15/07 100BASE-X Auxiliary Control Register Table 546: 100-BASE-X Auxiliary Control Register (Address 16d, 10h) Name Description Default Next Page 1 = Additional Next Page(s) follows 0 = Last page Reserved Message Page 1 = Message page 0 = Unformatted page...
Page 553: Table 547: 100Base-X Auxiliary Status Register (Address 17D, 11H)
Programmer’s Guide BCM5722 10/15/07 Extended FIFO Enable Controls the extended receive FIFO mechanism. This bit may have to be set if the Jumbo Packet Enable bit is set. 100BASE-X Auxiliary Status Register Table 547: 100BASE-X Auxiliary Status Register (Address 17d, 11h)
Page 554: Table 548: 100Base-X Receive Error Counter (Address 18D, 12H)
BCM5722 Programmer’s Guide 10/15/07 Remote Fault The PHY returns a 1 while its link partner is signaling a far-end fault condition. Otherwise, it returns a 0. False Carrier Detected The PHY returns a 1 in bit 5 of the extended status register if a false carrier has been detected since the last time this register was read.
Page 555: Table 549: 100Base-X False Carrier Sense Counter (Address 19D, 13H)
Programmer’s Guide BCM5722 10/15/07 100BASE-X False Carrier Sense Counter Table 549: 100BASE-X False Carrier Sense Counter (Address 19d, 13h) Name Description Default 15:8 SMII Overrun/Underrun Number of overruns/underruns since last read Counter [7:0] False Carrier Sense Number of false carrier sense events since last read...
Page 556: Table 551: Auxiliary Control/Status Register (Address 24D, 18H)
BCM5722 Programmer’s Guide 10/15/07 Auxiliary Control/Status Register Table 551: Auxiliary Control/Status Register (Address 24d, 18h) Name Description Default Jabber Disable 1 = Jabber function disabled in PHY 0 = Jabber function enabled in PHY Link Disable 1 = Link integrity test disabled in PHY...
Page 557 Programmer’s Guide BCM5722 10/15/07 HSQ:LSQ Extends or decreases the squelch levels for detection of incoming 10BASE-T data packets. The default squelch levels implemented are those defined in the IEEE standard. The high-squelch and low-squelch levels are useful for situations where the IEEE- prescribed levels are inadequate. The squelch levels are used by the CRS/link block to filter out noise and recognize only valid packet preambles and link integrity pulses.
Page 558: Table 552: Auxiliary Status Summary Register (Address 25D, 19H)
BCM5722 Programmer’s Guide 10/15/07 Auxiliary Status Summary Register The Auxiliary Status Summary register contains copies of redundant status bits found elsewhere within the MII register space. Descriptions for each of these individual bits can be found associated with the primary register descriptions.
Page 559: Table 553: Interrupt Register (Address 26D, 1Ah)
Programmer’s Guide BCM5722 10/15/07 Interrupt Register Table 553: Interrupt Register (Address 26d, 1Ah) Name Description Default FDX LED Enable Ignore when read INTR Enable Interrupt enable Cable Disconnect Mask Cable disconnect mask Reserved FDX Mask Full-duplex interrupt mask SPD Mask...
Page 560 BCM5722 Programmer’s Guide 10/15/07 SPD Mask When this bit is set, changes in operating speed does not generate an interrupt. Link Mask When this bit is set, changes in link status does not generate an interrupt. Interrupt Mask Master interrupt mask. When this bit is set, no interrupts will be generated, regardless of the state of the other mask bits.
Page 561: Table 554: Auxiliary Mode 2 Register (Address 27D, 1Bh)
Programmer’s Guide BCM5722 10/15/07 Auxiliary Mode 2 Register Table 554: Auxiliary Mode 2 Register (Address 27d, 1Bh) Name Description Default 15:12 Reserved 10BT Dribble Bit Correct 1 = Enable 0 = Disable Jumbo Packet Mode 1 = Enable 0 = Disable...
Page 562 BCM5722 Programmer’s Guide 10/15/07 Traffic Meter LED Mode When enabled, the Activity LEDs (ACTLED and FDXLED if full-duplex LED and interrupt LED modes are not enabled) does not blink based on the internal LED clock (approximately 80 ms on time). Instead, they blink based on the rate of receive and transmit activity.
Page 563: Table 555: 10Base-T Auxiliary Error And General Status Register (Address 28D, 1Ch)
Programmer’s Guide BCM5722 10/15/07 10BASE-T Auxiliary Error And General Status Register Table 555: 10BASE-T Auxiliary Error and General Status Register (Address 28d, 1Ch) Name Description Default 15:14 Reserved MDIX Status 0 = MDI is in use 1 = MDIX is in use...
Page 564 BCM5722 Programmer’s Guide 10/15/07 Manchester Code Error Indicates that a Manchester code violation was received. This bit is only valid during 10BASE-T operation. End of Frame Error Indicates that the end-of-frame (EOF) sequence was improperly received, or not received at all. This error bit is only valid during 10BASE-T operation.
Page 565: Table 556: Auxiliary Mode Register (Address 29D, 1Dh)
Programmer’s Guide BCM5722 10/15/07 Auxiliary Mode Register Table 556: Auxiliary Mode Register (Address 29d, 1Dh) Name Description Default 15:5 Reserved – – 000h Activity LED Disable 1 = Disable XMT/RCV Activity LED outputs 0 = Enable XMT/RCV Activity LED outputs...
Page 566: Table 557: Auxiliary Multiple Phy Register (Address 30D, 1Eh)
BCM5722 Programmer’s Guide 10/15/07 Auxiliary Multiple PHY Register Table 557: Auxiliary Multiple PHY Register (Address 30d, 1Eh) Name Description Default HCD_TX_FDX 1 = Auto-negotiation result is 100BASE-TX full-duplex HCD_T4 1 = Auto-negotiation result is 100BASE-T4 HCD_TX 1 = Auto-negotiation result is 100BASE-TX...
Page 567: Table 558: Broadcom Test Register (Address 31D, 1Fh)
10BASE-T Serial Mode Writing a 1 to bit 1 of the Auxiliary Mode register enables the 10BASE-T serial mode. Serial operation is not available in 100BASE-X mode Broadcom Test Register Table 558: Broadcom Test Register (Address 31d, 1Fh) Name Description Default...
Page 568: Table 559: Miscellaneous Control Register (Shadow Register 16D, 10H)
BCM5722 Programmer’s Guide 10/15/07 HADOW EGISTER ETAILED ESCRIPTION The following tables describe the shadow registers bits and their function. Shadow register access is enabled by writing a 1 to bit 7 of MII register 31 (1Fh). When non-shadow register access is required, write a 0 to bit 7 of MII register 31 (1Fh).
Page 569: Table 561: 100-Tx Port Cable Length
Programmer’s Guide BCM5722 10/15/07 MLT3 Detected The PHY returns a 1 in this bit whenever MLT3 signaling is detected. Cable Length 100X[2:0] The PHY provides the cable length for each port when a 100-TX link is established. Table 561: 100-TX Port Cable Length...
Page 570: Table 562: Auxiliary Status 3 Register (Shadow Register 28D, 1Ch)
BCM5722 Programmer’s Guide 10/15/07 Auxiliary Status 3 Register (Shadow Register) Table 562: Auxiliary Status 3 Register (Shadow Register 28d, 1Ch) Name Description Default 15:8 Noise[7:0] Current mean-squared error value, valid only if link is established Reserved 000h FIFO Consumption[3:0] Currently utilized number of nibbles in the receive FIFO 0000 MII shadow register bank 1 is accessed by setting MII register 1Fh bit 7 to a 1.
Page 571: Table 563: Auxiliary Mode 3 Register (Shadow Register 29D, 1Dh)
Programmer’s Guide BCM5722 10/15/07 Auxiliary Mode 3 Register (Shadow Register) Table 563: Auxiliary Mode 3 Register (Shadow Register 29d, 1Dh) Name Description Default 15:4 Reserved 000h FIFO Size Select[3:0] Currently selected receive FIFO size 0100 R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear after read operation.
Page 572 BCM5722 Programmer’s Guide 10/15/07 A p p e n di x A : Fl ow C on t ro l OTES Developers can refer to the IEEE 802.3 Annex 31B specification for detailed information on Ethernet flow control mechanisms. •...
Page 573: Figure 68: File Transfer Scenario: Ftp Session Begins
Programmer’s Guide BCM5722 10/15/07 RANSFER The client begins a FTP session (see Figure 68). The file size is very large and will take several minutes for a complete trans- fer, even at gigabit wire speed. File Transfer File Switch Gigabit Server...
Page 574: Figure 70: File Transfer Scenario: Speed Buffers Run Low
BCM5722 Programmer’s Guide 10/15/07 WITCH UFFERS The switch must wait/inhibit transmission to the Client (see Figure 70). During the pause interval, the Server is still sending packets to the Switch. The Switch will buffer some packets, but will eventually hit an internal threshold; memory will run short.
Page 575: Figure 71: File Transfer Scenario: Switch Backpressure
Programmer’s Guide BCM5722 10/15/07 WITCH ACKPRESSURE The Switch will jam ports configured with half-duplex link to slow frame transmission (see Figure 71). In this case, the Server connection must be half-duplex, and then the switch may apply backpressure to the port. The Switch will transmit a jamming pattern, which will prevent the Server from transmitting further packets.
Page 576: Figure 73: File Transfer Scenario: File Transfer Complete
BCM5722 Programmer’s Guide 10/15/07 RANSFER OMPLETE The Client has caught up with the transmission flow of the Server (see Figure 73). The Client’s RX buffers/memory is below the flow control threshold. The file is transfer is complete. This scenario was a worst-case cascade, where the pause delay propagated through the LAN.
Page 577 APM driver must call the APM BIOS once per second so the BIOS will not assume a system hang—watchdog type functionality. • Layer 4 is the APM aware Device Drivers and applications. NIC vendors like Broadcom provide power management capable device drivers. Add-in devices, like the BCM5722 Ethernet controller, have a power management capable device driver.
Page 578: Figure 75: Apm Architecture
BCM5722 Programmer’s Guide 10/15/07 APM-Aware Device Drivers APM-Aware Device Drivers APM-Aware Device Drivers O/S APM Driver Operating System APM interface Protected Mode APM interface Real Mode BIOS APM BIOS APM Device System Figure 75: APM Architecture APM manages system power consumption using six managed states (see...
Page 579: Figure 76: States For Power Consumption Management
Programmer’s Guide BCM5722 10/15/07 Full On APM_DISABLE APM_ENABLE SUSPEND LONG SUSPEND Hybernation Enabled Suspend WAKE_UP WAKE_UP RESUME STANDBY_CALL Standby Figure 76: States for Power Consumption Management The following register interfaces were taken from the APM BIOS specification and are intended as a quick reference (see Table 566).
Page 580: Table 567: Event Codes Quick Reference
BCM5722 Programmer’s Guide 10/15/07 Table 566: Function Codes Quick Reference (Cont.) AH Value Function Description 0x08 Set power state 0x09 Enable/disable power management 0x0A Get power status 0x0B Get power managed event 0x0C Get power state 0x0D Enable/disable device power management...
Page 581 Power Managed Device Driver—Vendor supplied software, which programs device-specific power management features. For example, the BCM5722 Ethernet controller needs to disable RX/TX RISC processor clocking for D3 states. The O/S does not have the necessary runtime code or understanding of the MAC’s architecture.
Page 582: Figure 77: Advanced Configuration And Power Interface (Acpi) Components
BCM5722 Programmer’s Guide 10/15/07 Kernel Power Managment Model Device Driver ACPI Driver Operating System BIOS ACPI Registers ACPI Tables ACPI BIOS System Hardware BIOS Figure 77: Advanced Configuration and Power Interface (ACPI) Components Bro adco m C orp or atio n...
Page 583: Figure 78: Os Power Management (Ospm) Global States
Programmer’s Guide BCM5722 10/15/07 The OS Power Management (OSPM) is responsible for global power state transitions. A global state is a platform wide con- figuration, which directs sleep and device power management state(s). The following global states are defined in the ACPI 2.0 specification (see...
Page 584: Figure 79: Acpi Sleep States
BCM5722 Programmer’s Guide 10/15/07 The ACPI Sleep States are subsets of the global ACPI G0–G3 states. For example, G0 working state corresponds to the S0 sleep state. The sleep states are defined in the ACPI 2.0 specification (see Figure 79): •...
Page 585: Table 568: Power Management Behavior For The Network Device Class
Programmer’s Guide BCM5722 10/15/07 The ACPI 2.0 specification defines power management behavior for device classes differently. For example, audio device states D0–D3, are not similar to modem device states. Refer to Appendix A of the ACPI 2.0 specification for a detailed dis- cussion of device power management.
Page 586 BCM5722 Programmer’s Guide 10/15/07 The PCI 2.2 specification states: “The Power Management Event (PME) signal is an optional hardware signal.” Wake capable networking devices will implement PME, so a change in system power management state can be requested. PME must be driven until system software clears the power management event. The PME signal is asynchronous to PCI clocking.
Page 587: Figure 80: Power Management Configuration During Post
Programmer’s Guide BCM5722 10/15/07 ® The ACPI specification refers to SMM as a legacy mode and prefers the native O/S (i.e., Microsoft Windows, Linux , etc.) to handle the interrupt. The essential problem with using SMI, resides in moving the processor into SMM mode; the native OS does not have visibility into the event.
Page 588: Figure 81: General Purpose Event Block
BCM5722 Programmer’s Guide 10/15/07 General Purpose Event Block GPE_STATUS_0 PME# GPE_ENB_0 GPE_STATUS_1 Power Button SCI# GPE_ENB_1 GPE_STATUS_2 Thermal GPE_ENB_2 Figure 81: General Purpose Event Block Bro adco m C orp or atio n Page 529 Document 5722-PG101-R...
Page 589: Figure 82: Pci-Specified Reset Interval
Programmer’s Guide BCM5722 10/15/07 Ap pe nd i x C: T i mi ng Con si d era t io ns ROM A PCI R XPANSION CCESS FTER ESET After the device is reset, ROM code in the device takes 20 ms to 50 ms (depending on the size of the boot firmware) to load the initial firmware code stored in the NVRAM.
Page 590: Figure 83: Gpio Hold Condition
Figure 83 shows the BCM5722 Ethernet controller GPIO hold condition. The GPIO pins hold their current output until the rising edge of reset. If the GPIO pins were tristated before the falling edge of RST, the pins will remain tri-stated. After the rising edge of reset, the GPIO pins will tri-state.
Page 591: Table 570: Terminology
PCI devices may optionally expose device specific programs to BIOS. For example, network devices may place PXE bootcode in their expansion ROM region. Host Coalescing A hardware block which the BCM5722 Ethernet controller status block. The hardware will drive a line interrupt or MSI. Interrupt Distribution Queue The BCM5722 Ethernet controller supports four interrupt distribution queues per class of service.
Page 592 BCM5722 Programmer’s Guide 10/15/07 Bro adco m C orp or atio n Page 533 GPIO Hold Condition Document 5722-PG101-R...
Page 593 Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

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