Table 348: Rx-Risc Timer Reference Register (Offset 0X6814); Table 349: Rx-Risc Semaphore Register (Offset 0X6818) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
RX-RISC T R
IMER EFERENCE
The Timer Reference register allows the RX-RISC to receive an event when the free-running Timer register counts up to this
value.
Note: This register is not applicable to the BCM5906 device.
Bit Field
31:0 RX-CPU Timer Reference RX-RISC Timer Event when Time stamp = RX-RISC Timer
RX-RISC S
EMAPHORE
The RX-RISC Semaphore register allows access to both internal RISC processors to a hardware semaphore mechanism.
Writes to the register indicates the preference to toggle the own/not own states of a single semaphore bit. Reads of this
register provide a 1 if that register owns the semaphore, and a 0 otherwise. To obtain the semaphore, the normal operation
is a loop containing a write 0 followed by a read. Exit the loop when the read returns nonzero. To release the semaphore,
the normal operation is to write 0.
Bit Field
31:1 Reserved
0 RX-CPU Semaphore bit
S EEPROM A
ERIAL
Note: This register is not applicable to the BCM5906 and BCM5787 devices.
This 32-bit register is used by the RISCs in conjunction with the Serial EEPROM Data Register to read and/or write serial
EEPROM data. The address register specifies the address and the direction of the transfer. When the transfer is complete
(for either a read or a write), the complete bit is set.
To use this register pair to read the serial EEPROM, set the address and ensure the read/write bit is set in the address
register. Loop reading the address register until the complete bit is set. When it is read the data from the data register. Clear
the complete bit by writing the bit. No other transfer will occur when the complete bit is set. The Device ID must be
programmed to select the appropriate device (A2 must be 0 for 128K/256Kx8 device).
To use this register pair to write the serial EEPROM, place the data into the data register. Then write the address into the
address register ensuring that the write bit is clear. Loop reading the address register until the complete bit is set. When it
is, the write is complete. Clear the complete bit by writing the bit. No other transfer will occur when the complete bit is set. It
is the responsibility of software to control the timing between successive read/write access to the serial EEPROM.
Document 5722-PG101-R
R
EGISTER

Table 348: RX-RISC Timer Reference Register (Offset 0x6814)

Description
Reference. Reset to all 1.
R (O
EGISTER FFSET

Table 349: RX-RISC Semaphore Register (Offset 0x6818)

Description
–
–
R (O
DDRESS EGISTER
Bro adco m Co rp or atio n
(O 0 6814)
FFSET X
0 6818)
X
0 6838)
FFSET X
BCM5722
Init Access
0 R/W
Init Access
0 RO
0 R/W
General Control Registers Page 340