Power Control) - Broadcom BCM5722 Programmer's Manual

BCM5722
Table 509: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 001, 10BASE-T) (Cont.)
Bit Field
5 SQE Enable Mode
4 10BASE-T No Dribble When enabled, the PHY rounds down to the nearest nibble
3 Reserved
2:0 Shadow Register
Select
A C
UXILIARY ONTROL
P C )
OWER ONTROL
Table 510: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 010,
Bit Field
15:6 Reserved
5 Super Isolate
4:3 Reserved
2:0 Shadow Register
Select
Page 447 Transceiver Registers
Description
Writing a 1 to this bit enables SQE mode. Writing a 0 disables
it.This bit is valid only during 10BASE-T operation.
• 1 = Enable SQE.
• 0 = Disable SQE.
when dribble bits are present on the 10BASE-T input stream.
• 1 = Correct 10BASE-T dribble nibble.
• 0 = Normal operation.
The Auxiliary Control Register provides access to eight
registers using a shadow technique. These three bits written
define which set of 13 upper bits is used. No setup is
required. Register reads are determined by the previous
write operation.
• 000 = Normal Operation
• 001 = 10 BASE-T Register.
• 010 = Power Control Register
• 011 = Reserved.
• 100 = Misc Test Register 1
• 101 = Misc Test Register 2
• 110 = Reserved.
• 111 = Misc Control Register
R (PHY_A
EGISTER DDR

Power Control)

Description
–
N/A
Write as 1, ignore on read.
The Auxiliary Control Register provides access to eight
registers using a shadow technique. These three bits
written define which set of 13 upper bits is used. No setup
is required. Register reads are determined by the
previous write operation.
• 000 = Normal Operation
• 001 = 10 BASE-T Register.
• 010 = Power Control Register
• 011 = Reserved.
• 100 = Misc Test Register 1
• 101 = Misc Test Register 2
• 110 = Reserved.
• 111 = Misc Control Register
Bro adco m C orp or atio n
= 0 1, R _A = 18
X EG DDR
Programmer's Guide
10/15/07
Init Access
0 R/W
0 R/W
0 RO
000 R/W
, S = 010,
H HADOW
Init Access
00Eh R/W
0 R/W
10 R/W
000 R/W
Document 5722-PG101-R