Read Dma Control Registers; Read Dma Mode Register (Offset 0X4800); Table 307: Read Dma Control Registers-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only; Table 308: Read Dma Control Registers-Bcm5906 Only - Broadcom BCM5722 Programmer's Manual

BCM5722
R DMA C
EAD ONTROL
Table 307: Read DMA Control Registers—BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754,
Offset
0x4800–0x4803
0x4804–0x4807
0x4808–0x4bff
Note: For the BCM5906 device only, the RDMA "debug" registers listed are all read-only. Reads to these registers
return internal state values. Do not write to the RDMA debug registers.
Offset
0x4800–0x4803
0x4804–0x4807
0x4808–0x480b
0x480c–0x4b0f
0x4810–0x481f
0x4820–0x4823
0x4824–0x4827
0x4828–0x484b
0x484c–0x4bff
R DMA M R
EAD ODE
Bit Field
31:29 Reserved
28 Hardware IPv6 Post-DMA Enable
(BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757 only)
Reserved (other devices)
27 Hardware IPv4 Post-DMA Enable
26 Post-DMA Debug Enable
Page 311

Read DMA Control Registers

R
EGISTERS
BCM5787 Only
Registers
Read DMA Mode
Read DMA Status
Reserved
Table 308: Read DMA Control Registers—BCM5906 Only
Registers
Read DMA Mode
Read DMA Status
Reserved
RDMA debug registers 1
Reserved
RDMA debug registers 2
Reserved
RDMA debug registers 3–10
Reserved
(O 0
EGISTER FFSET X

Table 309: Read DMA Mode Register (Offset 0x4800)

Description
–
Enable hardware LSO post-DMA processing for IPv6
Packets.
–
Enable hardware LSO post-DMA processing for IPv4
Packets.
When this bit is set, the Send Data Completion state
machine will be halted if the Post-DMA bit of the Send BD
is set.
Bro adco m C orp or atio n
4800)
Programmer's Guide
10/15/07
Init Access
0 RO
0 R/W
0 RO
0 R/W
0 R/W
Document 5722-PG101-R