Programmer's Guide
10/15/07
Auxiliary Mode Register
Bit
Name
15:5
Reserved
4
Activity LED Disable
3
Link LED Disable
2
Reserved
1
Block TXEN Mode
0
Reserved
R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear after read
operation. Use default values of reserved bit(s) when writing to reserved bit(s).
Activity LED Disable
When set to 1, disables the ACTLED output pin. When 0, ACTLED output pin is enabled.
Link LED Disable
When set to 1, disables the Link LED output pin. When 0, Link LED output is enabled.
Block TXEN Mode
When this mode is enabled, short IPGs of 1, 2, 3 or 4 TXC cycles all result in the insertion of two IDLEs before the beginning
of the next packet's JK symbols.
Document
5722-PG101-R
Table 556: Auxiliary Mode Register (Address 29d, 1Dh)
R/W
Description
–
–
R/W
1 = Disable XMT/RCV Activity LED outputs
0 = Enable XMT/RCV Activity LED outputs
R/W
1 = Disable Link LED output
0 = Enable Link LED output
–
–
R/W
1 = Enable Block TXEN mode
0 = Disable Block TXEN mode
–
–
Bro adco m Co rp or atio n
Transceiver Registers (BCM5906/BCM5906M)
BCM5722
Default
000h
0
0
0
0
0
Page 506
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