Bcm5757, Bcm5754, Bcm5787 Only; Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only; Table 293: Memory Arbiter Status Register (Offset 0X4004)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M; Table 294: Memory Arbiter Trap Address Low Register (Offset 0X4008)-Bcm5722, Bcm5755, Bcm5755M, Bcm5756M, Bcm5757, Bcm5754, Bcm5787 Only - Broadcom BCM5722 Programmer's Manual

BCM5722
M A S
EMORY RBITER
BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 O
Table 293: Memory Arbiter Status Register (Offset 0x4004)—BCM5722, BCM5755, BCM5755M, BCM5756M,
Bit Field
31:21 Reserved
20 DMAW 2 Addr Trap
19:17 Reserved
16 SDI Addr Trap
15:13 Reserved
12 RDI2 Addr Trap
11 RDI1 Addr Trap
10 RQ Addr Trap
9 Reserved
8 PCI Addr Trap
7 Reserved
6 RX RISC Addr Trap
5 DMAR1 Addr Trap
4 DMAW 1 Addr Trap
3 RX-MAC Addr Trap
2 TX-MAC Addr Trap
1:0 Reserved
M A T
EMORY RBITER
BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 O
Table 294: Memory Arbiter Trap Address Low Register (Offset 0x4008)—BCM5722, BCM5755, BCM5755M,
Bit Field
31:21 Reserved
20:0 MA Trap Addr Low
Page 303 Memory Arbiter Registers
R (O
TATUS EGISTER

BCM5757, BCM5754, BCM5787 Only

A L
RAP DDRESS OW

BCM5756M, BCM5757, BCM5754, BCM5787 Only

Description
–
Memory Arbiter Trap Address Low.
Bro adco m C orp or atio n
0 4004)—BCM5722, BCM5755,
FFSET X
Description
–
DMA Write 2 Memory Arbiter request trap.
–
Send Data Initiator Memory Arbiter request trap.
–
Receive Data Initiator 2 Memory Arbiter request
trap.
Receive Data Initiator 1 Memory Arbiter request
trap.
Receive List Placement Memory Arbiter request
trap.
–
PCI Memory Arbiter request trap.
–
RX RISC Memory Arbiter request trap.
DMA Read 1 Memory Arbiter request trap.
DMA Write 1 Memory Arbiter request trap.
Receive MAC Memory Arbiter request trap.
Transmit MAC Memory Arbiter request trap.
–
R (O
EGISTER FFSET
Programmer's Guide
NLY
Init
0
0
0
0
0
0 4008)—BCM5722,
X
NLY
Init
0
Document 5722-PG101-R
10/15/07
Access
RO
W2C
RO
W2C
R/W
W2C
W2C
W2C
R/W
W2C
R/W
W2C
W2C
W2C
W2C
W2C
RO
Access
RO
R/W