Broadcom BCM5722 Programmer's Manual page 298

BCM5722
This mailbox register provides two functions:
• Whenever the host writes to this register, the Interrupt State is cleared, regardless of what value is written to this
register. This applies to both the internal interrupt state, and the maskable external interrupt state (INTA). For instance,
if an interrupt-causing event had previously occurred, but interrupts were masked (i.e., the Mask Interrupt bit in the
Miscellaneous Host Control Register was set when the event occurred), an interrupt would be pending internally.
However, writing any value to Interrupt Mailbox 0, would clear that internally pending interrupt. Thus, when interrupts
were later unmasked, INTA would not be asserted due to that event, because the event would have been cleared by the
write to this register.
• Whenever In_ISR bits in this register contain a nonzero value, it indicates to the BCM5722 Ethernet controller that host
software is in its interrupt processing routine (ISR). This causes the device to use the during interrupt coalescing
registers as opposed to the non-during interrupt coalescing registers. In addition, since the device thinks the host is
running its ISR, the device will not assert an interrupt if a status block is written back while this register contains a
nonzero value. This provides host software with the flexibility of another mechanism to reduce interrupts (see
Coalescing Control Registers" on page
Since interrupts are prevented when this register is a nonzero value, and since interrupts are cleared whenever this register
is written (even if it is written to 0), care must be taken by the host driver to ensure that events that normally cause interrupts
are not lost. In other words, if this register is set to a nonzero value during the ISR, and then set to 0 near the end of the ISR,
host software should ensure that any events that occurred while in the ISR are noted. The host could do this by checking
the status block again at the bottom of the ISR and scheduling another interrupt processing routine if the status block was
updated with events that had not been previously handled by the host driver (see
page 185).
R BD S
ECEIVE TANDARD
The Receive BD Standard Producer Ring Index register contains the index of the next buffer descriptor for the standard
producer ring that will be produced in the host for the NIC to DMA into NIC memory. Host software writes this register
whenever it updates the standard producer ring. This register must be initialized to 0.
R BD R
ECEIVE ETURN
The Receive BD Return Ring Index register contains the index of last the buffer descriptor for return ring 1 that has been
consumed. Host software writes this register whenever it updates the return ring 1. This register must be initialized to 0.
R BD R
ECEIVE ETURN
This register is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, and BCM5757 devices only.
The Receive BD Return Ring Index register contains the index of last the buffer descriptor for return ring 2 that has been
consumed. Host software writes this register whenever it updates the return ring 2. This register must be initialized to 0.
R BD R
ECEIVE ETURN
This register is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, and BCM5757 devices only.
The Receive BD Return Ring Index register contains the index of last the buffer descriptor for return ring 3 that has been
consumed. Host software writes this register whenever it updates the return ring 3. This register must be initialized to 0.
Page 239 High-Priority Mailboxes
292).
P R
RODUCER ING
R 1 C I
ING ONSUMER
R 2 C I
ING ONSUMER
R 3 C I
ING ONSUMER
Bro adco m C orp or atio n
I R (O
NDEX EGISTER
R (O
NDEX EGISTER FFSET
R (O
NDEX EGISTER FFSET
R (O
NDEX EGISTER FFSET
Programmer's Guide
"Other Configuration Controls" on
0 268–0 26F)
FFSET X X
0 284–0 287)
X X
0 28C–0 28F)
X X
0 294–0 297)
X X
Document 5722-PG101-R
10/15/07
"Host