Table 438: Tlp Status Register (Offset 0X7C60); Table 439: Data Link Control Register (Offset 0X7D00) - Broadcom BCM5722 Programmer's Manual

BCM5722
TLP D R
EBUG EGISTER
Note: This register is not applicable to the BCM5906 device.
Bit Field
31 A4 Device Indication Bit
30 B1 Device Indication Bit
29:0 Reserved
D L C
ATA INK ONTROL
This register is reset only by POR.
Bit Field
31:28 Reserved
27 CQ26554 disable bit
(BCM5906 /
BCM5906M A2 and
later only)
Reserved (all others)
26:25 Reserved
24 PME Turn Off Message
Handling Fix CQ11211
23 Enable Data Link Layer
Retry Logic Fix
CQ11121
22 Power Mgmt State
Machine L0s Lockup
Fix CQ11080
21 Enable Flow Control
Credit Checking Fix
CQ10674
20 Enable L1 to L0
Transition when Device
is Configured to D3 Hot
CQ10453
Page 395 PCIe Registers
(O 0 7C6C)
FFSET X

Table 438: TLP Status Register (Offset 0x7C60)

Description
Indicates whether the device is A4 chip
Indicates whether the device is B1 chip
R (O
EGISTER FFSET

Table 439: Data Link Control Register (Offset 0x7D00)

Description
Write as 0, ignore when read.
1: Disable fix in dma_cmplt sm for CQ26554
0: Enable fix in dma_cmplt sm for CQ26554.
Write as 0, ignore when read
Write as 0, ignore when read
Set this bit to 1 to enable the fix.
Set to 1 to enable the fix.
Enable fix to transition out of L0s when link experiencing
recovery.
• 1 = Disable fix
• 0 = Enable fix
Enable this bit to check MPS or actually advertised credit.
• 1 = Disable fix
• 0 = Enable fix
Enable this fix to transition back to L1 after waked up and
D state is set at D3 state:
• 1 = Disable fix
• 0 = Enable fix
Bro adco m C orp or atio n
0 7D00)
X
Programmer's Guide
10/15/07
Init Access
1 for A4, RO
0 for other
versions
1 for B1, RO
0 for other
versions.
0 RO
Init Access
0 –
0 RW
–
0 –
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
Document 5722-PG101-R