Section 3: Hardware Architecture; Theory Of Operation; Figure 3: Functional Block Diagram - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
S e c t i o n 3 : H a rdw a r e A rchi t e c t ur e
T O
HEORY OF PERATION
Figure 3 shows the major functional blocks and interfaces of the BCM5722 Ethernet controllers. There are two packet flows:
MAC-transmit and receive. The device's DMA engine bus-masters packets from host memory to device local storage, and
vice-versa. The host bus interface is compliant with PCIe standards. The RX MAC moves packets from the integrated PHY
into device internal memory. All incoming packets are checked against a set of QOS rules and then categorized. When a
packet is transmitted, the TX MAC moves data from device internal memory to the PHY. Both flows operate independently
of each other in full-duplex mode. An on-chip RISC processor is provided for running value-added firmware that can be used
for custom frame processing. The on-chip RISC operates independently of all the architectural blocks; essentially, RISC is
available for the auxiliary processing of data streams.
Physical Layer
Transceiver
Document 5722-PG101-R
Transmit
Receive
GMII
GMII
Receive
Rx
MAC FIFO
Statistics
Transmit
Tx
MAC FIFO
Boot
Processor
Boot ROM
LED
PLL
Control
125-MHz Clock
LED Signals

Figure 3: Functional Block Diagram

Bro adco m Co rp or atio n
Rx Frame Buffer
Memory/RISC
Scratch Pad Memory
Rule
Check
Memory
Arbiter
SSRAM Control
EEPROM Control
NVRAM
SSRAM
Interface Interface
Queue
Memory
Tx Frame Buffer
Memory
Send BD RING
Registers
Receive BD RING
DMA Descriptor
Frame Buffer
Manager
Read
Read
FIFO
DMA
Write
Write
FIFO
DMA
Ring Controllers
Host Coalescing
Queue Management
System Management
Control
SMBus
Hardware Architecture
BCM5722
Config
PCIe Bus
PCIe
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