BCM5722
I
M
R
NTERRUPT
ASK
Table 515: Interrupt Mask Register (PHY_Addr = 0x1, Reg_Addr = 1Bh)
Bit
Field
15:0
Interrupt Mask Vector
S
C
1 (PHY_A
PARE
ONTROL
Table 516: Spare Control 1 Register (Address 1Ch, Shadow Value 00010)
Bit
Field
15
Write Enable
14:10
Shadow Register Selector
9:1
Reserved
0
Link LED Mode
Write Enable
During a write to this register, setting Spare Control 1 register bit 15 to a 1 allows writing to bits [7:0] of this register. For
reading the values of bits [9:0], perform an MDIO write with bit 15 set to a 0 and preferred shadow values in bits [14:10]. The
next MDIO read of register address 1Ch contains the preferred shadow register values in bits [9:0].
Shadow Register Selector
Bits [14:10] of this register must be set to 00010 to enable read/write to the Spare Control 1 register address 1Ch.
Link LED Mode
Bit 0 of MII register 1Ch with shadow value 00010 selects the link LED mode. When this bit is set, it enables the link LED
mode. The LINKSPD2/LINKSPD1 are Link/Speed LED and SLAVE LED is LINK LED to indicate a link for 10BASE-T,
100BASE-TX or 1000BASE-T. When this bit is cleared, the LINKSPD2, LINKSPD1, and SLAVE are in their normal mode.
Page 455
Transceiver Registers
(PHY_A
EGISTER
DDR
Description
When bit n of the Interrupt Mask Register is written to 1, the
interrupt corresponding to the same bit in the Interrupt
Status Register is masked. The status bits still operate
normally when the interrupt is masked, but do not generate
an interrupt output. When the bit is written to 0, the interrupt
is unmasked.
• 1 = Interrupt masked, status bits operate normally.
• 0 = Interrupt enabled, status bits operate normally.
= 0
1, R
DDR
X
Description
• 1 = Write bits [9:0].
• 0 = Read bits [9:0].
00010 = Spare Control 1 register.
Write as 00h, ignore when read.
• 1 = Enable link LED mode.
• LINKSPD[2:1] = speed.
• 00 = 1000BASE-T link.
• 01 = 100BASE-TX link.
• 10 = 10BASE-T link or no link.
• SLAVE = Active low 10/100/1000BASE-T link.
• 0 = Normal link LED mode.
Bro adco m C orp or atio n
= 0
1, R
_A
= 1B
X
EG
DDR
_A
= 1C
, S
EG
DDR
H
Programmer's Guide
)
H
Init
11...1
00010
)
HADOW
B
Init
0
00010
00h
0
Document 5722-PG101-R
10/15/07
Access
R/W
Access
R/W
R/W
R/W
R/W
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