Table 152: Message Control Register (Offset 0Xea) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
M C
ESSAGE ONTROL
This 16-bit register provides system software control over MSI. After reset, MSI is disabled (bit 0 is cleared) and the function
requests servicing via its INTA pin. System software can enable MSI by setting bit 0 of this register to a 1. System software
is permitted to modify the Message Control register's read/write bits and fields. A device driver is not permitted to modify the
read/write bits and fields.
Bit Field
15:8 Reserved
7 64-bit Address Capable Indicates that the device is capable of generating a 64-bit
6:4 Multiple Message
Enable
3:1 Multiple Message
Capable
0 MSI Enable
Document 5722-PG101-R
R (O
EGISTER FFSET

Table 152: Message Control Register (Offset 0xEA)

Description
–
message address. This bit is hardwired to 1 because the device
is 64-bit message address capable.
System software writes to this field to indicate the number of
allocated messages (equal to or less than the number of
requested message). The number of allocated messages is
aligned to a power of two. When MSI is enabled, a device will
be allocated at least one message. The encoding is as follows:
Encoding
000
001
010
011
100
101
110
111
System software reads this field to determine the number of
requested messages. The number of requested messages
must be aligned to a power of two. The encoding is as follows:
Encoding
000
001
010
011
100
101
110
111
If 1, the function is permitted to use MSI to request service and
is prohibited from using the INTA pin. If 0, the device is
prohibited from using MSI. System software sets this bit to
enable MSI. A device driver is prohibited from writing to this bit.
Bro adco m Co rp or atio n
0 EA)
X
# Messages Allocated
1
2
4
8
16
32
Rsvd
Rsvd
# Messages Allocated
1
2
4
8
16
32
Rsvd
Rsvd
Message Signaled Interrupts Capabilities
BCM5722
Init Access
0 RO
1 RO
000 R/W
000 RO
0 R/W
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