Table 342: Mode Control Register (Offset 0X6800) - Broadcom BCM5722 Programmer's Manual

BCM5722
Field
0x6894–0x6897
0x6898–0x689B
0x689C–0x689F
0x68A0–0x68A3
0x68A4–0x68A7
0x68A8–0x68AF
0x68B0–0x68B3
0x68B4–0x68ff
M C R
ODE ONTROL EGISTER
Bit Field
31:29 Reserved
28 Interrupt on Flow Attention
27 Interrupt on DMA Attention
26 Interrupt on MAC Attention
25 Interrupt on RX RISC
Attention
Reserved (BCM5906 only)
24 Reserved
23 Receive No Pseudo-header
Checksum
22 Reserved
21 NVRAM Write Enable
20 Send No Pseudo-header
Checksum
19:18 Reserved
17 Host Send BDs
16 Host Stack Up
15 Force 32-bit PCI
14 Don't Interrupt on Receives Never cause an interrupt on receive return ring producer
13 Don't Interrupt on Sends
12 Reserved
Page 333 General Control Registers
Table 341: General Control Registers—BCM5906 Only (Cont.)
Description
Reserved
Chip mode Register
Energy_Det Timer Register
Reserved
Power management Debug Register
Reserved
Energy_Det Control Register
Reserved
(O 0 6800)
FFSET X

Table 342: Mode Control Register (Offset 0x6800)

Description
–
Cause a host interrupt when an enabled flow attention occurs. 0
Cause a host interrupt when an enabled DMA attention
occurs.
Cause a host interrupt when an enabled MAC attention
occurs.
Cause a host interrupt when an enabled RX RISC attention
occurs.
–
–
Do not include the pseudoheader in the TCP or UDP
checksum calculations. To obtain the correct checksum, the
driver must add the TCP/UDP checksum field to the pseudo-
header checksum.
–
The host must set this bit before attempting to update the
Flash or SEEPROM
Do not include the pseudoheader in the TCP or UDP
checksum calculations. To obtain the correct checksum, the
driver must seed the TCP/UDP checksum field with the
pseudoheader checksum.
–
Use host-based BD rings instead of NIC-based BD rings.
The host stack is ready to receive data from the NIC.
Force PCI operation as if on a 32-bit PCI bus.
updates.
Never cause an interrupt on send BD ring producer updates. 0
–
Bro adco m C orp or atio n
Programmer's Guide
10/15/07
Init Access
0 RO
R/W
0 R/W
0 R/W
0 R/W
0 RO
0 RO
0 R/W
0 RO
0 R/W
0 R/W
00
0 R/W
0 R/W
0 R/W
0 R/W
R/W
0
Document 5722-PG101-R