Host Coalescing Status Register (Offset 0X3C04); Receive Coalescing Ticks Registers (Offset 0X3C08); Send Coalescing Ticks Register (Offset 0X3C0C); Table 285: Host Coalescing Status Register (Offset 0X3C04) - Broadcom BCM5722 Programmer's Manual

BCM5722
H C
OST OALESCING
Bit Field
31:3 Reserved
2 Error
1:0 Reserved
R C
ECEIVE OALESCING
The value in this register can be used to control how often the status block is updated (and how often interrupts are
generated) due to receiving packets. The value in this register controls how many ticks, in units of 1 µs each, get loaded in
an internal receive tick timer register. The timer will be reset to the value of this register and will start counting down after
every status block update (regardless of the reason for the status block update). The timer is only reset after status block
updates, and is not reset after any given packet is received. When the timer reaches 0, it will be considered to be in the
expired state. Once the counter is in the expired state, a status block update will occur if a packet had been received and
copied to host memory (via DMA) since the last status block update.
This register must be initialized by host software. A value of 0 in this register disables the receive tick coalescing logic. In
this case, status block updates will occur for receive event only if the Receive Max Coalesced BD value is reached. Of
course, status block updates for other reasons (e.g., transmit events) will also include any updates to the receive indices.
By setting the value in this register to a high number, a software device driver can reduce the number of status block updates
and interrupts that occur due to receiving packets. This will generally increase performance in hosts that are under a high
degree of stress and whose RISCs are saturated due to handling a large number of interrupts from the network controller.
For host environments where receive interrupt latency needs to be very low, and the host is not close to be saturated, it is
recommended that this register be set to 1.
S C
END OALESCING
The value in this register can be used to control how often the status block is updated (and how often interrupts are
generated) according to the completion of transmit events. The value in this register controls how many ticks, in units of 1 µs
each, get loaded in an internal transmit tick timer register. The timer will be reset to the value of this register and will start
counting down, after every status block update (regardless of the reason for the status block update). The timer is only reset
after status block updates, and is not reset after a transmit event completes. When the timer reaches 0, it will be considered
to be in the expired state. Once the counter is in the expired state, a status block update will occur if a transmit event has
occurred since the last status block update. In this case, a transmit event is defined by an update to one of the device's Send
BD Consumer Indices. It should be noted that a Send Consumer Index increments whenever the data associated with a
particular packet has been successfully moved (via DMA) across the bus, rather than when the packet is actually transmitted
over the Ethernet wire.
This register must be initialized by host software. A value of 0 in this register disables the transmit tick coalescing logic. In
this case, status block updates will occur for transmit events only if the Send Max Coalesced BD value is reached, or if the
BD_FLAG_COAL_NOW bit is set in a send BD. Status block updates for other reasons (e.g., receive events) will also include
any updates to the send indices.
By setting the value in this register to a high number, a software device driver can reduce the number of status block updates,
and interrupts, that occur due to transmit completions. This will generally increase performance in hosts that do not require
Page 295 Host Coalescing Control Registers
S R (O
TATUS EGISTER

Table 285: Host Coalescing Status Register (Offset 0x3C04)

Description
–
Host Coalescing error status.
–
T R
ICKS EGISTERS
T R (O
ICKS EGISTER
Bro adco m C orp or atio n
0 3C04)
FFSET X
(O 0 3C08)
FFSET X
0 3C0C)
FFSET X
Programmer's Guide
10/15/07
Init Access
0 RO
RO
0 RO
Document 5722-PG101-R