Receive Max Coalesced Bd Count (Offset 0X3C10); Send Max Coalesced Bd Count (Offset 0X3C14) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
their send buffers to be freed quickly. For host environments that do require their send buffers to be recovered quickly, it is
recommended that this register be set to 0.
R M C
ECEIVE AX OALESCED
This register contains the maximum number of receive return ring BDs that must filled in by the device before the device will
update the status block due to a receive event.
Whenever the device completes the reception of a packet, it will fill in a receive return ring BD, and then increment an internal
receive coalesce BD counter. When this internal counter reaches the value in this register, a status block update will occur.
This counter will be reset (i.e., zeroed) whenever a status block update occurs regardless of the reason for the status block
update.
This register must be initialized by host software. A value of 0 in this register disables the receive max BD coalescing logic.
In this case, status block updates will occur for receive packets only via the Receive Coalescing Ticks mechanism. Status
block updates for other reasons (e.g., transmit events) will also include any updates to the receive indices.
For simplicity, if a host wanted to get a status block update for every received packet, the host driver should just set this
register to a value of 1. On the other hand, by setting the value in this register to a high number, a software device driver can
reduce the number of status block updates and interrupts that occur due to receiving packets. This can increase performance
in hosts that are under a high degree of stress and whose RISCs are saturated due to handling a large number of interrupts
from the network controller. However, in lower traffic environments, there is no guarantee that consecutive packets will be
received in a timely manner. Therefore, for those environments, it is recommended that the Receive Coalescing Ticks
register are used to make sure that status block updates due to receiving packets are not delayed for an infinite amount of
time.
S M C
END AX OALESCED
This register contains the maximum number of send BDs that must be processed by the device before the device will update
the status block due to the transmission of packets.
Whenever the device completes the DMA of transmit packet buffer, it increments an internal send coalesce BD counter.
When this internal counter reaches the value in this register, a status block update will occur. This counter will be reset (i.e.
zeroed) whenever a status block update occurs regardless of the reason for the status block update.
This register must be initialized by host software. A value of 0 in this register disables the send max BD coalescing logic. In
this case, status block updates will occur for receive packets only via the Send Coalescing Ticks mechanism. Of course,
status block updates for other reasons (e.g., receive events) will also include any updates to the send indices.
For simplicity, if a host wanted to get a status block update for every transmitted packet, the host driver could just set this
register to a value of 1. On the other hand, by setting the value in this register to a high number, a software device driver can
reduce the number of status block updates and interrupts that occur due to transmitting packets. This can increase
performance in hosts that are under a high degree of stress and whose RISCs are saturated due to handling a large number
of interrupts from the network controller. However, in lower traffic environments, there is no guarantee that consecutive
packets will be transmitted in a timely manner. Therefore, for those environments, it is recommended that the Send
Coalescing Ticks register are used to make sure that status block updates due to transmitting packets are not delayed for
an infinite amount of time.
Note: For the BCM5906 only, when either the normal Data SBD ring send-count or the ISO SBD ring send-count
reaches the value of this register, a status block update is triggered.
Document 5722-PG101-R
BD C (O
OUNT FFSET
BD C (O
OUNT FFSET
Bro adco m Co rp or atio n
0 3C10)
X
0 3C14)
X
Host Coalescing Control Registers
BCM5722
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