Table 240: Vlan Tag Register For Tcp Segmentation (Offset 0Xcf0); Table 241: Vlan Tag Register For Tcp Segmentation (Offset 0Xcf0) - Broadcom BCM5722 Programmer's Manual

BCM5722
Table 239: DMA Flags Register for TCP Segmentation (Offset 0xCEC) (Cont.)
Bit Field
2 Invoke Processor
1 Don't Generate CRC
0 No Byte Swap
VLAN T R
AG EGISTER FOR

Table 240: VLAN Tag Register for TCP Segmentation (Offset 0xCF0)

Bit Field
31:16 Reserved
15:0 VLAN Tag
P -DMA C
RE OMMAND

Table 241: VLAN Tag Register for TCP Segmentation (Offset 0xCF0)

Bit Field
31 READY
30 PASS
29 SKIP
28:7 Reserved
6:0 BD_Index
Page 275 TCP Segmentation Control Registers
Description
Invoke Processor. Clear the PASS bit of the entry queued
to the SDCQ, so that SDC will invoke the CPU.
• If the packet is created by hardware, this bit will be the
same as bit 9 (BD_FLAG_CPU_POST_DMA) of the
flag field in the Send BD.
• If the packet is created by firmware, it will be up to CPU
whether it needs to post-process the data.
Do not Generate CRC. Pass through Send Buffer
Descriptor flag.
No Byte Swap. Set to disable endian byte swap on data
from PCI bus.
TCP S
EGMENTATION
Description
–
VLAN tag to be inserted into the Frame Header if bit 7 of
DMA Flags register is set.
E R
XCHANGE EGISTER FOR
Description
The CPU sets this bit to tell the SDI that the DMA
address, length, flags, and VLAN tag are valid and the
request is ready to be go. The CPU polls this bit to be
clear for the completion of the request.
If this bit is set to 0, the CPU will be responsible for
processing the buffer descriptor.
The CPU sets this bit to 1 to inform the SDI that the TCP
segmentation is completed, and the BD_Index can be
incremented.
–
The internal current buffer descriptor pointer that the
hardware/firmware is servicing.
Bro adco m C orp or atio n
(O 0 CF0)
FFSET X
TCP S
EGMENTATION
Programmer's Guide
10/15/07
Init Access
0 R/W
0 R/W
0 R/W
Init Access
0 RO
0 R/W
(O 0 CF4)
FFSET X
Init Access
0 R/W
1 R/W
0 R/W
0 RO
0 R/W
Document 5722-PG101-R