Table 511: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 100, Misc Test 1) - Broadcom BCM5722 Programmer's Manual

Host programmer interface specification for the netxtreme and netlink family of highly integrated media access controllers
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Programmer's Guide
10/15/07
A
C
UXILIARY
ONTROL
M
T
1)
ISC
EST

Table 511: Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 100, Misc Test 1)

Bit
Field
15
Lineside [Remote]
Loopback Enable
14:12
Reserved
11
Lineside [Remote]
Loopback Tri-state
10:5
Reserved
4
Swap RX MDIX
3
TXHalfout
2:0
Shadow Register
Select
Document
5722-PG101-R
R
(PHY_A
EGISTER
Description
Setting bit 15 enables lineside [remote] loopback of the
copper receive packet back out through the MDI transmit
path.
• 1 = Enable lineside [remote] loopback from MDI (cable
end) receive packet, through PCS and back to MDI
transmit packet.
• 0 = Disable loopback.
Write as 0, ignore on read.
Setting bit 11 tri-states the receive MII pins when the device
is in lineside [remote] loopback mode.
• 1 = Tri-state the receive MII pins when lineside [remote]
loopback is enabled.
• 0 = Lineside [remote] loopback packets appear on MII.
Write as 0, ignore on read
When this bit is set to 1, the transmitter and receiver operate
on the same twisted-pair. This function is for use in a test
mode in which the transmitter output is detected by the
receiver attached to the same pair.
• 1 = RX and TX operate on same pair.
• 0 = Normal operation.
Setting this bit to 1 reduces the output of the transmitter to half
of its normal amplitude when operating in 10 Mbit or
100BASE-TX mode. Setting it to 0 restores full amplitude
operation. This function is for use in a test mode in which an
unterminated output delivers a reflected signal with twice the
amplitude of a terminated output.
• 1 = Transmit 10BASE-T and 100BASE-T at half amplitude.
• 0 = Normal operation.
The Auxiliary Control Register provides access to eight
registers using a shadow technique. These three bits written
define which set of 13 upper bits is used. No setup is required.
Register reads are determined by the previous write
operation.
• 000 = Normal Operation
• 001 = 10 BASE-T Register.
• 010 = Power Control Register
• 011 = Reserved.
• 100 = Misc Test Register 1
• 101 = Misc Test Register 2
• 110 = Reserved.
• 111 = Misc Control Register
Bro adco m Co rp or atio n
= 0
1, R
_A
DDR
X
EG
= 18
, S
DDR
H
HADOW
Init
0
000
00h
0
0
000
Transceiver Registers
BCM5722
= 100,
Access
R/W
R/W
R/W
RO
R/W
R/W
Page 448

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