Table 381: Auxiliary Smbus Master Status Register (Offset 0X6C40) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
A SMB
UXILIARY US

Table 381: Auxiliary SMBus Master Status Register (Offset 0x6C40)

Bit Field
31:8 Reserved
7 CRC/PEC Error
6:5 Reserved
4 Failed
3 Bus Collision
2 Device Error
1 SMBus Attention
0 Master Busy
Document 5722-PG101-R
M S R
ASTER TATUS EGISTER
Description
–
• 0 = No CRC/PEC Error detected.
• 1 = CRC/PEC Error Detected. This bit is set only by
hardware and can be reset by writing a 1 to this
position.
–
• 0 = SMBus Attention not caused by KILL bit.
• 1 = Source of the SMBus attention is a failed bus
transaction, set when KILL bit in SMB Master Control
register is set. This bit is set only by hardware and can
be reset by writing a one to this position.
• 0 = SMBus Attention not caused by transaction
collision.
• 1 = Source of SMBus Attention was a transaction
collision. This bit is set only by hardware and can be
reset by writing a 1 to this position.
• 0 = SMBus interrupt not caused by transaction error.
• 1 = Source of SMBus interrupt was the generation of a
SMBus transaction error. This bit is set only by
hardware and can be reset by writing a 1 to this
position. Transaction errors are usually caused by:
- Illegal command field
• Unclaimed cycle
• Master device time-out
• 0 = SMBus attention not caused by Master command
completion.
• 1 = Source of SMBus attention was the completion of
the last Master command. This bit is set only by
hardware and can be reset by writing a 1 to this
position.
• 0 = SMBus Controller Master interface is not
processing a command.
• 1 = Indicates that the SMBus controller master
interface is in the process of completing a command.
None of the other SMBus Master registers should be
accessed if this bit is set.
Bro adco m Co rp or atio n
(O 0 6C40)
FFSET X
BCM5722
Init Access
0 RO
0 R/W
0 RO
0 R/W
0 R/W
0 R/W
0 R/W
0 RO
ASF Support Registers Page 362