Table 128: Pci State Register (Offset 0X70) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
PCI S R
TATE EGISTER
The PCI State register is used to control several functions within the device associated with the PCI interface.
Note: The Enable PCI State Register Read/Write Capability bit of the Miscellaneous Host Control register must
be enabled to write the PCI State register from the PCI configuration cycle (see
Register (Offset 0x68)" on page
Bit Field
31:16 Reserved
15 Config Retry
14 Reserved
13 Retry Same DMA (other
devices)
12 3.3VAux Present
11:9 Max PCI Target Retry
8 Flat View
7 VPD Available
6 PCI Expansion ROM Retry Force PCI Retry for accesses to Expansion ROM region, if
5 PCI Expansion ROM
Desired
4:2 Reserved
1 PCI INT state
0 Reserved
a. Bit-enabled R/W through PCI configuration space.
Document 5722-PG101-R
(O 0 70)
FFSET X
204).

Table 128: PCI State Register (Offset 0x70)

Description
–
When asserted, forces all config access to be retried.
–
When set, prevents internal arbitration logic from switching to
the other DMA engine after a retry cycle.
This bit reads as 1 when the 3.3V auxiliary power source is
present.
Indicates the number of PCI clock cycles before Retry occurs,
in multiple of 8. At reset, this field is set to 001.
Asserted if the Base Address Register presents a 32 MB PCI
Address Map Flat View, otherwise, indicates a 64 KB PCI
Address Map Standard View.
This bit reads as 1 if the VPD region of the NVRAM can be
accessed by the host.
enabled.
Enable PCI ROM Base Address Register to be visible to the
PCI host.
–
Reflect the state of PCI INTA
–
Bro adco m Co rp or atio n
0
Broadcom Vendor-Specific Capabilities
BCM5722
"Miscellaneous Host Control
Init Access
0 RO
1 R/W
0 RO
0 R/W
0 RO
a
001 RO
a
0 RO
0 RO
a
0 RO
a
0 RO
0 RO
1 RO
0 RO
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