Broadcom BCM5722 Programmer's Manual page 21

Programmer's Guide
10/15/07
RXMBUF Cluster Free Enqueue Register (Offset 0x5CC8) ............................................................... 328
RDIQ FTQ Write/Peek Register (Offset 0x5CFC)............................................................................... 328
Message Signaled Interrupt Registers ................................................................................................... 330
MSI Mode Register (Offset 0x6000) ................................................................................................... 330
MSI Status Register (Offset 0x6004) .................................................................................................. 330
MSI FIFO Access Register (Offset 0x6008)........................................................................................ 331
General Control Registers....................................................................................................................... 332
Mode Control Register (Offset 0x6800) .............................................................................................. 333
Miscellaneous Configuration Register (Offset 0x6804)....................................................................... 335
Miscellaneous Local Control Register (Offset 0x6808) ....................................................................... 336
Timer Register (Offset 0x680C) .......................................................................................................... 337
RX-RISC Event Register (Offset 0x6810) ........................................................................................... 338
RX-RISC Timer Reference Register (Offset 0x6814) ......................................................................... 340
RX-RISC Semaphore Register (Offset 0x6818).................................................................................. 340
Serial EEPROM Address Register (Offset 0x6838) ............................................................................ 340
Serial EEPROM Data Register (Offset 0x683C) ................................................................................. 341
Serial EEPROM Control Register (Offset 0x6840).............................................................................. 341
MDI Control Register (Offset 0x6844)................................................................................................. 342
Serial EEPROM Delay Register (Offset 0x6848) ................................................................................ 342
RX CPU Event Enable Register (Offset 0x684C) ............................................................................... 343
Wake-on-LAN Registers .......................................................................................................................... 345
WOL Mode Register (Offset 0x6880).................................................................................................. 345
WOL Config Register (Offset 0x6884) ................................................................................................ 345
WOL State Machine Status Register (Offset 0x6888)......................................................................... 346
Miscellaneous CableSense Control Register (Offset: 0x6890) ........................................................... 347
Fast Boot Program Counter Register (Offset 0x6894) ........................................................................ 348
Chip Mode Register (Offset: 0x6898) ................................................................................................. 349
Energy Detect Timer Register (Offset: 0x689C) ................................................................................. 350
Miscellaneous Clock Control Register (Offset: 0x68A0) ..................................................................... 351
Power Management Debug Register (Offset: 0x68A4)....................................................................... 352
Energy_Det Control Register (Offset: 0X68B0) .................................................................................. 353
ASF Support Registers ............................................................................................................................ 355
ASF Control Register (Offset 0x6C00)................................................................................................ 356
SMBus Input Register (Offset 0x6C04)............................................................................................... 357
Document 5722-PG101-R
Bro adco m Co rp or atio n
BCM5722
Page xxi