Table 490: Phy Extended Control Register (Phy_Addr = 0X1, Reg_Addr = 10H) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
Table 489: IEEE Extended Status Register (PHY_Addr = 0x1, Reg_Addr = 0Fh) (Cont.)
Bit Field
12 1000BASE-T Half-
Duplex Capability
11:0 Reserved
PHY E C
XTENDED ONTROL

Table 490: PHY Extended Control Register (PHY_Addr = 0x1, Reg_Addr = 10h)

Bit Field
15 MAC/PHY Interface
Mode
14 Disable Automatic MDI
Crossover
13 Transmit Disable
12 Interrupt Disable
11 Force Interrupt
10 Bypass 4B/5B
Encoder/Decoder
9 Bypass Scrambler/
Descrambler
8 Bypass MLT3 Encoder/
Decoder
Document 5722-PG101-R
Description
The BCM5722 Ethernet controller is capable of
1000BASE-T half-duplex operation, and returns a 1 when
bit 12 of the IEEE extended Status Register is read.
• 1 = 1000BASE-T half-duplex capable.
• 0 = Not 1000BASE-T half-duplex capable.
Write as 0, ignore on read.
R (PHY_A
EGISTER
Description
The MAC/PHY interface is GMII.
• 1 = TBI (10-bit Interface).
• 0 = GMII.
The automatic MDI crossover function can be disabled by
writing a 1 to bit 14 of the PHY Extended Control Register.
When the bit is written to 0, the BCM5722 Ethernet controller
performs the automatic MDI crossover function (see
MDI Crossover" on page
• 1 = Automatic MDI crossover disabled.
• 0 = Automatic MDI crossover enabled.
The transmitter can be disabled by writing a 1 to bit 13 of the
PHY Extended Control Register. The transmitter outputs (TRD ±
{0...3}) are forced into a high impedance state.
• 1 = Transmitter outputs disabled.
• 0 = Normal operation.
• 1 = Interrupt status output disabled.
• 0 = Interrupt status output enabled.
• 1 = Force interrupt status to active.
• 0 = Normal operation.
The 100BASE-TX 4B/5B encoder/decoder can be bypassed by
writing a 1 to bit 10:
• 1 = Transmit and receive 5B codes over MII pins.
• 0 = Normal MII.
The 100BASE-TX stream cipher function can be disabled by
writing a 1 to bit 9 of the PHY Extended Control Register. The
stream cipher function can be re-enabled by writing a 0 to this
bit.
• 1 = Scrambler and descrambler disabled.
• 0 = Scrambler and descrambler enabled.
The 100BASE-TX MLT3 encoder and decoder can be
bypassed by writing a 1 to bit 8 of the PHY Extended Control
Register. NRZ data is transmitted and received on the cable.
The MLT3 encoder can be re-enabled by writing a 0 to this bit.
• 1 = Bypass NRZI/MLT3 encoder and decoder.
• 0 = Normal operation.
Bro adco m Co rp or atio n
= 0 1, R _A
DDR X EG
35).
BCM5722
Init Access
1 RO
H
0 RO
= 10 )
DDR H
Init Access
0 R/W
0 R/W
"Automatic
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Transceiver Registers Page 428