Broadcom BCM5722 Programmer's Manual page 586

BCM5722
PCI
PME
The PCI 2.2 specification states:
"The Power Management Event (PME) signal is an optional hardware signal."
Wake capable networking devices will implement PME, so a change in system power management state can be requested.
PME must be driven until system software clears the power management event. The PME signal is asynchronous to PCI
clocking. Wake events are reported by devices when a Wake_Int bit is set in the PMCSR register. PME is enabled/disabled
by setting a Wake_En bit in the PMCSR register. The PMCSR register is not device/application specific.
3.3 V
AUX
The PCI 2.2 specification states:
"An optional 3.3 volt auxiliary power source delivers power to PCI add-in cards for generation of power management events
when the main power to the card has been turned off by software."
The 3.3 Vaux is pin 14 on Side A of a PCI connector. A device will use Vaux while in a low-power state, like D3.
S P
LOT OWER
A 3.3V or 5.0V power supply for add-in cards. This is the main power supply for the device while in the full power D0 power
management state. Several pins on the PCI connector provide paths to the 5.0V or 3.3V power planes on the host
motherboard. Refer to the PCI 2.2 specification for the PCI connector pin-out. The choice and use of slot power is based
upon the hardware application.
SMI/SCI
Intel processors support a mode call System Management Mode (SMM). SMM is completely transparent to a native OS and
operates in another processor address space. System BIOS may implement event handlers for power management in SMM
address space. SMM mode is invoked via a System Management Interrupt (SMI). A generated SMI will cause the following
actions:
• The system will enable System Management memory (SMRAM). Normal RAM is disabled.
• Processor registers are saved off to SMRAM.
Processor registers are initialized with SMM settings.
•
• Processor jumps to entry point in SMRAM, where the SMI handler is placed.
• Power management registers are queried to determine cause of SMI.
• SMM handler services the appropriate request.
• A Return from System Management Mode (RSM) instruction is issued.
• Processor restores registers saved in step #2.
• Normal RAM is enabled. SMRAM is disabled.
Page 527 PCI
Bro adco m C orp or atio n
Programmer's Guide
10/15/07
Document 5722-PG101-R