Table 400: Nvm Config 1 Register (Offset 0X7014) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
NVM C 1 R
ONFIG EGISTER
Bit Field
31 compat_bypass
30:28 PageSize
27 Address Lockout
Enable Status
26 Safe Erase
25 Flash Size
24 Protect Mode
23:22 Reserved
21:11 SEE_CLK_DIV
10:7 SPI_CLK_DIV
Document 5722-PG101-R
(O 0 7014)
FFSET X

Table 400: NVM Config 1 Register (Offset 0x7014)

Description
Enable the 5701 legacy SEEPROM interface to bypass this
interface.
These bits indicate the page size of the attached flash device.
They are set automatically depending on the chosen flash as
indicated by the strapping option pins. Page sizes are as follows:
• 000b = 256 bytes
• 001b = 512 bytes
• 010b = 1024 bytes
• 011b = 2048 bytes
• 100b = 4096 bytes
• 101b = 264 bytes
• 110b = Reserved
• 111b = Reserved
This bit will be set if the address lockout feature is active; it will be
clear otherwise. This bit is read only. Its state can be changed only
via a strapping option or bonding option.
When mimicking buffered behavior with an unbuffered Flash, this
bit controls whether a page erase occurs as the result of a write
first or a write last. If the bit is clear, then the erase will be issued
as part of the write first operation. If the bit is set, then the erase
shall be issued the first step in a write last operation. Clearing the
bit may result in higher performance, as the erase occurs
concurrent with the write more operations. Setting the bit may
result in improved data integrity, as the erase is not started until
the flash controller is ready to write back the entire page.
Set this bit for a 1-MB device or 0 for a 512-KB device.
HARD_RESET, GRC_RESET, and Setting command register bit
0 will reset this bit to pin strap.
Set this bit for flash devices that implement a write protect
function.
HARD_RESET, GRC_RESET, and Setting command register bit
0 will reset this bit to pin strap.
–
This field is a divisor used to create all 1x times for all SEEPROM
interface I/O pin timing definitions. A value of 0 means that an SCL
transitions at a minimum of each CORE_CLK rising edge. The
equation to calculate the clock frequency for SCL is:
CORE_CLK /((SEE_CLK_DIV + 1) * 4)
Note: SCL is four times slower than 1x time. The default value
corresponds to 1.42MHz
This field is a divisor used to create all 1x times for all Flash
Interface I/O pin timing definitions. A divisor of 0 means that an
SCK transitions at minimum of each CORE_CLK rising edge. The
equation to calculate the clock frequency for SCK is:
CORE_CLK /((SPI_CLK_DIV +1) *2)
Note: SCK is two times slower than 1x time. The default value
corresponds to 6.6 MHz.
Bro adco m Co rp or atio n
Init
0
Depends on Flash
Strapping
Depends on
Address Lockout
Enable State
1
pin
pin
00b
16
4
Non-Volatile Memory Interface Registers
BCM5722
Access
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
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