Sign In
Upload
Manuals
Brands
Broadcom Manuals
Recording Equipment
BCM5722KFB1G
Broadcom BCM5722KFB1G Manuals
Manuals and User Guides for Broadcom BCM5722KFB1G. We have
1
Broadcom BCM5722KFB1G manual available for free PDF download: Programmer's Manual
Broadcom BCM5722KFB1G Programmer's Manual (593 pages)
Host Programmer Interface Specification for the NetXtreme and NetLink Family of Highly Integrated Media Access Controllers
Brand:
Broadcom
| Category:
Recording Equipment
| Size: 7 MB
Table of Contents
Table of Contents
3
Section 11: Interrupt Processing/Section 12: Bcm5722 Ethernet Controller Register Definitions
11
Table of Contents
19
L Fist of Igures
36
Section 1: about this Document
60
Terms Used in this Document
60
Example Code
61
Functional Overview
61
Notational Conventions
61
Operational Characteristics
61
Registers and Bits
61
Table 1: Pseudocode
61
Related Documents
63
Introduction
64
Section 2: Introduction
64
Feature Comparison
65
Table 2: Family Features
65
Revision Levels
67
Table 3: Family Revision Levels
67
BCM5755 and BCM5755M Macs
68
Figure 1: Typical BCM5755-Based NIC Board Block Diagram
69
Table 4: BCM5755 NIC Part Component Breakdown
69
Typical Application
69
BCM5754, BCM5754M, BCM5787, and BCM5787M Macs
70
Figure 2: Typical BCM5754-Based NIC Board Block Diagram
71
Table 5: BCM5754 NIC Part Component Breakdown
71
Typical Application
71
Programming the BCM5722 Ethernet Controllers
72
Figure 3: Functional Block Diagram
73
Section 3: Hardware Architecture
73
Theory of Operation
73
Figure 4: Receive Data Path
74
Receive Data Path
74
RX Engine
74
Rx Fifo
74
Rules Checker
75
RX List Initiator
75
RX List Placement
75
Figure 5: Transmit Data Path
76
Transmit Data Path
76
Tx Fifo
76
Tx Mac
76
Isochronous Send Ring (BCM5906, BCM5906M Only)
77
Figure 6: ISO SBD Internal Block Diagram
78
Internal Block Diagram
78
Iso Sdi
78
Figure 7: Time-Sync Packet
79
Table 6: ISO SDI Block
79
Figure 8: Sample Traffic Flow with ISO and Normal Data Packets
81
Table 7: BCM5906 Status Block
82
Table 8: ISO Send BD
82
Table 9: Example of Setting up an ISO Stream
83
Figure 9: DMA Read Engine
84
Figure 10: DMA Write Engine
85
Figure 11: ASF System Architecture
86
Figure 12: Smbus Start and Stop Conditions
88
Figure 13: Two Masters Arbitrate for Smbus
89
Figure 14: Master Stops Transaction after Slave Naks
89
Figure 15: Smbus Transaction Phases
90
Figure 16: SMB_CLOCK Period (Master Mode)
90
Figure 17: Host Coalescing Engine
92
Figure 18: Media Independent Interface
95
GMII Block
96
Figure 19: GMII Block
97
Figure 20: MDI Register Interface
98
Management Data Clock
98
Management Data Input/Output
98
Management Data Interrupt
98
Management Register Block
98
MDIO Register Interface
98
Bist
99
Jtag
99
Self-Test
99
Overview
100
Section 4: NVRAM Configuration
100
Self-Boot
100
Descriptor Rings
101
Section 5: Common Data Structures
101
Theory of Operation
101
Figure 21: Generic Ring Diagram
102
Producer and Consumer Indices
102
Ring Control Blocks
103
Send Rings
103
Table 10: Ring Control Block Format
103
Table 11: Flag Fields for a Ring
103
Figure 22: Transmit Ring Data Structure Architecture Diagram
104
Send Buffer Descriptors
105
Table 12: Send Buffer Descriptors Format
105
Table 13: Defined Flags for Send Buffer Descriptors
105
Receive Rings
106
Figure 23: Receive Return Ring Memory Architecture Diagram
107
Receive Producer Ring
108
Receive Return Rings
108
Table 14: Receive Return Rings
108
Receive Buffer Descriptors
109
Table 15: Receive Descriptors Format
109
Table 16: Defined Flags for Receive Buffers
109
Table 17: Defined Error Flags for Receive Buffers
111
And BCM5754M Devices
112
Status Block
112
Status Block Format
112
Table 18: Status Block Format for BCM5787, BCM5787M, BCM5906, BCM5906M, BCM5754
112
Table 19: Status Block Format for BCM5755 and BCM5755M Devices
113
Table 20: Status Word Flags
113
Device Statistics
115
Host Interrupts
115
MAC Statistics
115
MIB Network Interface Card Statistics
115
NIC BD Coalescing Thresholds
115
Table 21: Send Data Initiator Host Interrupts Statistics
115
Table 22: Send Data Initiator NIC BD Coalescing Thresholds Statistics
115
Table 23: Receive List Placement NIC BD Coalescing Thresholds Statistics
115
DMA Resources
116
MAC Resources
116
Table 24: Send Data Initiator DMA Resources Statistics
116
Table 25: Receive List Placement DMA Resources Statistics
116
Table 26: Send Data Initiator MAC Resources Statistics
116
Table 27: Receive List Placement MAC Resources Statistics
116
Class of Service Statistics
117
Interface Statistics in Receive Placement State Machine
117
Table 28: Send Data Initiator Class of Service Statistics
117
Table 29: Receive List Placement Class of Service Statistics
117
Table 30: Interface Statistics in Rx List Placement Engine
117
Figure 24: Receive Buffer Descriptor Cycle
119
Figure 25: Receive Producer Ring RCB Setup
121
Figure 26: Mailbox Registers
123
Table 32: Receive BD Rules Control Register
125
Table 33: Receive BD Rules Value/Mask Register
126
Figure 27: Class of Service Example
127
Table 34: Frame Format with 802.1Q VLAN Tag Inserted
128
Figure 28: Overview Diagram of RX Flow
129
Figure 29: RSS Receive Processing Sequence
131
Figure 30: Relationships between All Components of a Send Ring
134
Figure 31: Max_Len Field in Ring Control Block
134
Figure 32: Relationship between Send Buffer Descriptors
135
Figure 33: Scatter Gather of Frame Fragments
137
Figure 34: Transmit Data Flow
139
Figure 35: Basic Driver Flow to Send a Packet
140
Table 35: Recommended BCM5722 Ethernet Controller Memory Pool Watermark Settings
144
Table 36: Recommended BCM5722 Ethernet Controller Low Watermark Maximum Receive Frames' Settings
144
Table 37: Recommended BCM5722 Ethernet Controller Standard Ring Initialization Settings for Internal Memory Only
145
Settings
147
Table 38: Recommended BCM5722 Ethernet Controller Host Coalescing Tick Counter Settings
147
Table 39: Recommended BCM5722 Ethernet Controller Host Coalescing Frame Counter Settings
147
Table 40: Recommended BCM5722 Ethernet Controller Max Coalesced Frames During Interrupt Counter
147
Figure 36: Firmware Image Moved to Scratch Pad/Rxmbuf
152
Table 41: Addressing Perspectives
152
Table 42: Mac Address Registers
155
Table 43: Multicast Hash Table Registers
157
Table 44: BCM5755/BCM5755M Address Map
160
Table 45: BCM5787/BCM5787M/BCM5754/BCM5754M Address Map
162
Table 46: BCM5906/BCM5906M Address Map
164
Figure 37: Local Contexts
167
Figure 38: Header Type Register 0Xe
168
Figure 39: Header Region Registers
169
Figure 40: Device-Specific Registers
171
Table 47: Device Specific Registers
172
Figure 41: Register Indirect Access
173
Figure 42: Indirect Memory Access
175
Figure 43: Low-Priority Mailbox Access for Indirect Mode
177
Figure 44: Standard Memory Mapped I/O Mode
178
Figure 45: Memory Window Base Address Register
179
Table 48: PCI Address Map Standard View
179
Figure 46: Standard Mode Memory Window
180
Figure 47: Flat Mode Memory Map
182
Table 49: PCI Address Map Flat View
183
Figure 48: Flat Mode Memory Map
186
Figure 49: Techniques for Accessing BCM5722 Ethernet Controller Local Memory
187
Figure 50: PCI Command Register
188
Figure 51: PCI Base Address Register
189
Figure 52: PCI Base Address Register Bits Read in Standard Mode
189
Figure 53: PCI Base Address Register Bits Read in Flat Mode
190
Table 50: PCI Registers
190
Figure 54: Read and Write Channels of DMA Engine
192
Table 51: PCI -X Registers
194
Figure 55: Power State Transition Diagram
196
Table 52: GPIO Usage for BCM5700/BCM5701 Power Management for Broadcom Drivers
198
Table 53: GPIO Usage for BCM5703C/BCM5703S and Later Power Management for Broadcom Drivers
198
Table 54: BCM5722 Ethernet Controller Power Pins
198
Table 55: Power Management Registers
200
Table 56: Endian Example
201
Table 57: Storage of Big-Endian Data
201
Table 58: Storage of Little-Endian Data
201
Figure 56: Default Translation (no Swapping) on 64-Bit PCI
203
Figure 57: Default Translation (no Swapping) on 32-Bit PCI
203
Table 59: RCB (Big Endian 32-Bit Format)
203
Figure 58: Word Swap Enable Translation on 32-Bit PCI (no Byte Swap)
204
Figure 59: Byte Swap Enable Translation on 32-Bit PCI (no Word Swap)
204
Figure 60: Byte and Word Swap Enable Translation on 32-Bit PCI
204
Table 60: Big-Endian Internal Packet Data Format
205
Table 61: 64-Bit PCI Bus (WSD = 0, BSD = 0)
206
Table 62: 32-Bit PCI Bus (WSD = 0, BSD = 0)
206
Table 63: 64-Bit PCI Bus (WSD = 0, BSD = 1)
206
Table 64: 32-Bit PCI Bus (WSD = 0, BSD = 1)
206
Table 65: 64-Bit PCI Bus (WSD = 1, BSD = 0)
207
Table 66: 32-Bit PCI Bus (WSD = 1, BSD = 0)
207
Table 67: 64-Bit PCI Bus (WSD = 1, BSD = 1)
207
Table 68: 32-Bit PCI Bus (WSD = 1, BSD = 1)
207
Table 69: Send Buffer Descriptor (Big-Endian 64-Bit Format)
208
Table 70: Send Buffer Descriptor (Big-Endian 32-Bit Format)
208
Table 71: Send Buffer Descriptor (Little-Endian 32-Bit Format) with no Swapping
209
Table 72: Send Buffer Descriptor (Little-Endian 32-Bit Format) with Word Swapping
209
Table 73: Send Buffer Descriptor (Big-Endian 32-Bit Format) with Byte Swapping
209
Table 74: Send Buffer Descriptor (Big-Endian 32-Bit Format) with Word and Byte Swapping
210
Figure 61: WOL Functional Block Diagram
218
Table 75: Required Memory Regions for WOL Pattern
219
Figure 62: Comparing Ethernet Frames against Available Patterns (10/100 Ethernet WOL)
221
Figure 63: Unused Rows and Rules Must be Initialized with Zeros
222
Table 76: 10/100 Mbps Mode Frame Patterns Memory
222
Table 77: Frame Control Field for 10/100 Mbps Mode
223
Table 78: Example of Splitting 10/100 Mbps Frame Data in Pattern Data Structure
223
Table 79: Firmware Mailbox Initialization
224
Table 80: Recommended Settings for PHY Auto-Negotiation
224
Table 81: WOL Mode Clock Inputs
225
Table 82: Magic Packet Detection Logic Enable
225
Table 83: PHY WOL Mode Control Registers
226
Table 84: Integrated MAC WOL Mode Control Registers
227
Receive MAC
230
Table 85: Transmit MAC Watermark Recommendation
230
Table 86: Pause Quanta
230
Transmit MAC
230
Statistics Block
231
Table 87: Keep_Pause Recommended Value
231
Table 88: Statistic Block
231
Integrated Phys
232
PHY Auto-Negotiation
232
Register Quick Cross Reference
232
Table 89: PHY Flow Control Registers
232
Flow Control Initialization Pseudocode
233
Integrated Macs
233
Table 90: Integrated MAC Flow Control Registers
233
Description
236
Host Coalescing
236
Operational Characteristics
236
Section 11: Interrupt Processing
236
Registers
237
Table 91: Interrupt-Related Registers
237
Figure 64: Traditional Interrupt Scheme
238
Msi
238
Traditional Interrupt Scheme
238
Figure 65: Message-Signaled Interrupt Scheme
239
Message Signaled Interrupt
239
Figure 66: MSI Data Field
240
MSI Address
240
MSI Data
240
PCI Configuration Registers
240
Firmware
241
Host Coalescing Engine
241
Basic Driver Interrupt Processing Flow
242
Figure 67: Basic Driver Interrupt Service Routine Flow
242
Flowchart for Servicing an Interrupt
242
Interrupt Procedure
243
Broadcom Mask Mode
244
Broadcom Tagged Status Mode
244
Clear Ticks on BD Events Mode
244
No Interrupt on DMAD Force
244
No Interrupt on Force Update
244
Other Configuration Controls
244
PCI Configuration Registers
245
Section 12: BCM5722 Ethernet Controller Register Definitions
245
Table 92: PCI Configuration Register Summary
245
Device ID Register (Offset 0X02)
248
Table 93: Vendor ID Register (Offset 0X00)
248
Table 94: Device ID Register (Offset 0X02)
248
Vendor ID Register (Offset 0X00)
248
Table 95: Command Register (Offset 0X04)
249
Table 96: Status Register (Offset 0X06)
250
Table 97: Revision ID Register (Offset 0X08)
250
Table 100: Latency Timer Register (Offset 0X0D)
251
Table 101: Header Type Register (Offset 0X0E)
251
Table 98: Class Code Register (Offset 0X09)
251
Table 99: Cache Line Size Register (Offset 0X0C)
251
Table 102: bist Register (Offset 0X0F)
252
Table 103: Base Address Register 1/2 (Offset 0X10)
252
Table 104: Subsystem Vendor ID Register (Offset 0X2C)
253
Table 105: Subsystem ID Register (Offset 0X2E)
253
Table 106: Expansion ROM Base Address Register (Offset 0X30)
254
Table 107: Capabilities Pointer Register (Offset 0X34)
254
Table 108: Interrupt Line Register (Offset 0X3C)
254
Table 109: Minimum Grant Register (Offset 0X3E)
255
Table 110: Maximum Latency Register (Offset 0X3F)
255
Table 111: Power Management Capability Register (Offset 0X48)
256
Table 112: PM Next Capabilities Pointer Register (Offset 0X49)
256
Table 113: Power Management Capabilities Register (Offset 0X4A)
256
Table 114: Power Management Control/Status Register (Offset 0X4C)
257
Table 115: Power Management Data Register (Offset 0X4F)
258
Table 116: VPD Capability ID Register (Offset 0X50)
259
Table 117: VPD Next Capabilities Pointer Register (Offset 0X51)
259
Table 118: VPD Flag and Address Register (Offset 0X52)
259
Table 119: VPD Data Register (Offset 0X54)
260
Table 120: MSI Capability ID Register (Offset 0X58)
261
Table 121: Vendor-Specific Next Capabilities Pointer Register (Offset 0X59)
261
Table 122: Vendor-Specific Capabilities Length Register (Offset 0X5A)
261
Table 123: Reset Counters Register (Offset 0X5C)
261
Table 124: Device Serial no Lower DW Override Register (Offset: 0X60)
262
Table 125: Device Serial no Upper DW Override Register (Offset: 0X64)
262
Table 126: Miscellaneous Host Control Register (Offset 0X68)
263
Table 127: DMA Read/Write Control Register (Offset 0X6C)
264
Table 128: PCI State Register (Offset 0X70)
265
Table 129: PCI Clock Control Register
266
Table 130: Register Base Address Register (Offset 0X78)
268
Table 131: Memory Window Base Address Register (Offset 0X7C)
269
Table 132: Register Data Register (Offset 0X80)
270
Table 133: Memory Window Data Register (Offset 0X84)
270
Table 134: Expansion ROM BAR Size Register (0X88)
271
Table 135: Expansion ROM Address Register (Offset 0X8C)
271
Table 136: Expansion ROM Data Register (0X90)
272
Table 137: VPD Interface Register (Offset 0X94)
272
Table 138: UNDI Receive BD Standard Producer Ring Producer Index Mailbox (Offset 0X98)
273
Table 139: UNDI Receive Return Ring Consumer Index Mailbox (Offset 0Xa0)
273
Table 140: UNDI Send BD Producer Index Mailbox (Offset 0Xa8)
273
Table 141: Pcie Capability ID Register (Offset 0Xd0)
274
Table 142: Pcie Next Capabilities Pointer Register (Offset 0Xd1)
274
Table 143: Pcie Capabilities Register (Offset 0Xd2)
274
Table 144: Device Capabilities Register (Offset 0Xd4)
275
Table 145: Device Control Register (Offset 0Xd8)
276
Table 146: Device Status Register (Offset 0Xda)
277
Table 147: Link Capabilities Register (Offset 0Xdc)
278
Table 148: Link Control Register (Offset 0Xe0)
279
Table 149: Link Status Command Register (Offset 0Xe2)
279
Table 150: MSI Capability ID Register (Offset 0Xe8)
280
Table 151: MSI Next Capabilities Pointer Register (Offset 0Xe9)
280
Table 152: Message Control Register (Offset 0Xea)
281
Table 153: Message Address Register (Offset 0Xec)
282
Table 154: Message Data Register (Offset 0Xf4)
282
Table 155: Advanced Error Reporting Enhanced Capability Header Register (Offset 0X100)
283
Table 156: Uncorrectable Error Status Register (Offset 0X104)
283
Table 157: Uncorrectable Error Mask Register (Offset 0X108)
284
Table 158: Uncorrectable Error Severity Register (Offset 0X10C)
285
Table 159: Correctable Error Status Register (Offset 0X110)
286
Table 160: Correctable Error Mask Register (Offset 0X114)
286
Table 161: Advanced Error Capabilities and Control Register (Offset 0X118)
286
Table 162: Virtual Channel Enhanced Capability Header (Offset 0X13C)
287
Table 163: Port VC Capability Register (Offset 0X140)
287
Table 164: Port VC Capability Register 2 (Offset 0X144)
287
Table 165: Port VC Control Register (Offset 0X148)
287
Table 166: Port VC Status Register (Offset 0X14A)
288
Table 167: VC Resource Capability Register (Offset 0X14C)
288
Table 168: VC Resource Control Register (Offset 0X150)
288
Table 169: VC Resource Status Register (Offset 0X156)
288
Table 170: Device Serial no Enhanced Capability Header Register (Offset 0X160)
289
Table 171: Device Serial no Lower DW Register (Offset 0X164)
289
Table 172: Device Serial no Upper DW Register (Offset 0X168)
290
Table 173: Power Budgeting Enhanced Capability Header Register (Offset 0X16C)
290
Table 174: Power Budgeting Data Select Register (Offset 0X170)
290
Table 175: Power Budgeting Data Register (Offset 0X174)
291
Table 176: Power Budgeting Capability Register (Offset 0X178)
291
Table 177: Firmware Power Budgeting Register 1 (Offset 0X17C)
292
Table 178: Firmware Power Budgeting Register 2 (Offset 0X17E)
292
Table 179: Firmware Power Budgeting Register 3 (Offset 0X180)
293
Table 180: Firmware Power Budgeting Register 4 (Offset 0X182)
293
Table 181: Firmware Power Budgeting Register 5 (Offset 0X184)
294
Table 182: Firmware Power Budgeting Register 6 (Offset 0X186)
294
Table 183: Firmware Power Budgeting Register 7 (Offset 0X188)
295
Table 184: Firmware Power Budgeting Register 8 (Offset 0X18A)
295
Table 185: Pcie 1.1 Advisory Non-Fatal Error Masking (Offset: 0X18C)
296
Table 186: High-Priority Mailbox Registers
297
Table 187: High-Priority Mailbox Structure
297
BCM5754, BCM5787 Only
300
Table 188: Ethernet MAC Control Registers-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757
300
Table 189: Ethernet MAC Control Registers-BCM5906 Only
302
Table 190: Ethernet MAC Mode Register (Offset 0X400)
304
Table 191: Ethernet MAC Status Register (Offset 0X404)
305
Table 192: Ethernet MAC Event Enable Register (Offset 0X408)
306
Table 193: LED Control Register (Offset 0X40C)
306
Table 194: Ethernet MAC Address High Register (Offset 0X410)
308
Table 195: Ethernet MAC Address Low Register (Offset 0X414)
308
Table 196: WOL Pattern Pointer Register (Offset 0X430)
308
Table 197: WOL Pattern Configuration Register (Offset 0X434)
309
Table 198: Ethernet Transmit Random Backup Register (Offset 0X438)
309
Table 199: Receive MTU Size Register (Offset 0X43C)
309
Table 200: MI Communication Register (Offset 0X44C)
310
Table 201: MI Status Register (Offset 0X450)
310
Table 202: MI Mode Register (Offset 0X454)
311
Table 203: Autopolling Status Register (Offset 0X458)
311
Table 204: Transmit MAC Mode Register (Offset 0X45C)
312
Table 205: Transmit MAC Status Register (Offset 0X460)
312
Table 206: Transmit MAC Lengths Register (Offset 0X464)
313
Table 207: Receive MAC Mode Register (Offset 0X468)
313
Table 208: Receive MAC Status Register (Offset 0X46C)
315
Table 209: MAC Hash Register 0-3 (Offset 0X470)
315
Table 210: Receive Rules Control Register (Offset 0X480)
316
Table 211: Receive Rules Value/Mask Register (Offset 0X484)
317
Table 212: Receive Rules Configuration Register (Offset 0X500)
317
Table 213: Low Watermark Maximum Receive Frames Register (Offset 0X504)
317
Table 214: Ethernet Type Matching Value Register (Offset 0X510)
318
Table 215: Protocol ID Offset Register (Offset 0X514)
318
Table 216: Regulator Voltage Control Register (Offset 0X590)
319
Table 217: Indirection Table Register 0 (Offset: 0X630)
320
Table 218: Indirection Table Register 15 (Offset: 0X66C)
321
Table 219: Hash Key Register 0 (Offset: 0X670)
321
Table 220: Hash Key Register 9 (Offset: 0X694)
322
Table 221: Receive MAC Programmable Ipv6 Extension Header Register (0X6A0)
322
Table 222: Statistics Registers
323
Table 223: Send Data Initiator Control Registers-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
327
Table 224: Send Data Initiator Control Registers-BCM5906 Only
327
Table 225: Send Data Initiator Mode Register (Offset 0X0C00)-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
328
Table 226: Send Data Initiator Mode Register (Offset 0X0C00)-BCM590X Only
328
Table 227: Send Data Initiator Status Register (Offset 0X0C04)
329
Table 228: Send Data Initiator Statistics Control Register (Offset 0X0C08)
329
Table 229: Send Data Initiator Statistics Enable Mask Register (Offset 0X0C0C)
329
Table 230: Send Data Initiator Statistics Increment Mask Register (Offset 0X0C10)
330
Table 231: ISO Packet Transmit Support Register (Offset 0X0C20-0X0C23)-BCM5906 Only
330
Table 232: Local Network Time Clock (Offset 0X0C24-0X0C27)-BCM5906 Only
330
Table 233: Logged Local Network Time for Inbound/Outbound Time Sync Packet (Offset 0X0C28-0X0C2B)-BCM5906 Only
331
Table 234: Local Statistics Counters (Offset 0X0C80-0X0Cdf)
331
Table 235: TCP Segmentation Control Registers
332
Table 236: Lower Host Address Register for TCP Segmentation (Offset 0Xce0)
332
Table 237: Upper Host Address Register for TCP Segmentation (Offset 0Xce4)
332
Table 238: Length/Offset Register for TCP Segmentation (Offset 0Xce8)
332
Table 239: DMA Flags Register for TCP Segmentation (Offset 0Xcec)
333
Table 240: VLAN Tag Register for TCP Segmentation (Offset 0Xcf0)
334
Table 241: VLAN Tag Register for TCP Segmentation (Offset 0Xcf0)
334
Table 242: Send Data Completion Control Registers
335
Table 243: Send Data Completion Mode Register (Offset 0X1000)
335
Table 244: Post-DMA Command Exchange Register for TCP Segmentation (Offset 0X1008)
335
Table 245: Send BD Ring Selector Control Registers
336
Table 246: Send BD Ring Selector Mode Register (Offset 0X1400)
336
Table 247: Send BD Ring Selector Status Register (Offset 0X1404)
336
(Offset 0X1440) -BCM5906 Only
337
Table 248: Send BD Diagnostic Ring Selector Local NIC Send BD Consumer Index Registers (Offset 0X1440)-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
337
Table 250: Send BD Ring Selector Control Registers
338
Table 251: Send BD Initiator Mode Register (Offset 0X1800)
338
Table 252: Send BD Initiator Status Register (Offset 0X1804)
338
Table 253: Send BD Completion Control Registers
339
Table 254: Send BD Completion Mode Register (Offset 0X1C00)
339
Table 255: Receive List Placement Control Registers-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
340
Table 256: Receive List Placement Control Registers-BCM5906 Only
340
Table 257: Receive List Placement Mode Register (Offset 0X2000)
341
Table 258: Receive List Placement Status Register (Offset 0X2004)
341
Table 259: Receive List Placement Configuration Register (Offset 0X2010)
342
Table 260: Receive List Placement Statistics Control Register (Offset 0X2014)
342
Table 261: Receive List Placement Statistics Enable Mask Register (Offset 0X2018)
343
Table 262: Receive List Placement Statistics Increment Mask Register (Offset 0X201C)
344
Table 263: Local Statistics Counter (Offset for BCM5906 Only: 0X2203; Offset for All Others: 0X2200)
344
Table 264: Receive Data and Receive BD Initiator Control Registers
345
Table 265: Receive Data and Receive BD Initiator Mode Register (Offset 0X2400)
345
Table 266: Receive Data and Receive BD Initiator Status Register (Offset 0X2404)
346
Table 267: Receive Producer Ring Host Address High Register (Offset 0X2450)
346
Table 268: Receive Producer Ring Host Address Low Register (Offset 0X2454)
346
Table 269: Receive Producer Length/Flags Register (Offset 0X2458)
346
Table 270: Receive Producer Ring NIC Address (Offset 0X245C)
346
Table 271: Receive Data Completion Control Registers
347
Table 272: Receive Data Completion Mode Register (Offset 0X2800)
347
Table 273: Receive BD Initiator Control Registers
348
Table 274: Receive Data Initiator Mode Register (Offset 0X2C00)
348
Table 275: Receive BD Initiator Status Register (Offset 0X2C04)
348
Only
349
Table 276: Standard Receive BD Producer Ring Replenish Threshold Register (Offset 0X2C18)-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
349
Table 277: Standard Receive BD Producer Ring Replenish Threshold Register (Offset 0X2C18)-BCM5906
349
Table 278: Receive BD Completion Control Registers
350
Table 279: Receive BD Completion Mode Register (Offset 0X3000)
350
Table 280: Receive BD Completion Status Register (Offset 0X3004)
350
Table 281: NIC Standard Receive BD Producer Index (Offset 0X300C)
350
Host Coalescing Control Registers
351
Table 282: Host Coalescing Control Registers-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
351
Table 283: Host Coalescing Control Registers-BCM5906 Only
351
Host Coalescing Mode Register (Offset 0X3C00)
353
Host Coalescing Status Register (Offset 0X3C04)
354
Receive Coalescing Ticks Registers (Offset 0X3C08)
354
Send Coalescing Ticks Register (Offset 0X3C0C)
354
Table 285: Host Coalescing Status Register (Offset 0X3C04)
354
Receive Max Coalesced BD Count (Offset 0X3C10)
355
Send Max Coalesced BD Count (Offset 0X3C14)
355
Flow Attention Register (Offset 0X3C48)
356
Receive Max Coalesced BD Count During Interrupt (Offset 0X3C20)
356
Send Max Coalesced BD Count During Interrupt (Offset 0X3C24)
356
Status Block Base Address Register (Offset 0X3C44)
356
Status Block Host Address Register (Offset 0X3C38)
356
Table 286: Flow Attention Register (Offset 0X3C48)
356
NIC Diagnostic Return Rings Producer Index Registers 1-4 (Offset 0X3C80-0X3C8F)-BCM5722
357
NIC Receive BD Consumer Index Register (Offset 0X3C54-0X3C57)
357
Table 287: NIC Return Ring Producer Index Registers (Offset 0X3C80, 0X3C84, 0X3C88, and 0X3C8C)- BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
357
NIC Diagnostic Return Rings Producer Index Register (Offset 0X3C80-0X3C83)-BCM5906 Only
358
Table 288: NIC Return Ring Producer Index Register (Offset 0X3C80)-BCM5906 Only
358
NIC Diagnostic Send BD Consumer Index Register (Offset 0X3Cc0-0X3Cc3)
359
Table 289: NIC Send BD Consumer Index (Offset 0X3Cc0)-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
359
Table 290: NIC Send BD Consumer Index (Offset 0X3Cc0)-BCM5906 Only
359
Memory Arbiter Mode Register (Offset 0X4000)
360
Memory Arbiter Registers
360
Table 291: Memory Arbiter Registers
360
Table 292: Memory Arbiter Mode Register (Offset 0X4000)
360
BCM5756M, BCM5757, BCM5754, BCM5787 Only
362
BCM5757, BCM5754, BCM5787 Only
362
Table 293: Memory Arbiter Status Register (Offset 0X4004)-BCM5722, BCM5755, BCM5755M, BCM5756M
362
Table 294: Memory Arbiter Trap Address Low Register (Offset 0X4008)-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
362
BCM5756M, BCM5757, BCM5754, BCM5787 Only
363
Memory Arbiter Trap Address High Register (Offset 0X400C)-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
363
Table 295: Memory Arbiter Trap Address High Register (Offset 0X400C)-BCM5722, BCM5755, BCM5755M
363
Buffer Manager Control Registers
364
Table 296: Buffer Manager Control Registers-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
364
Table 297: Buffer Manager Control Registers - BCM5906 Only
364
BCM5757, BCM5754, BCM5787 Only
365
Buffer Manager Mode Register (Offset 0X4400)
365
Table 298: Buffer Manager Mode Register (Offset 0X4400)
365
Table 299: Buffer Manager Status Register (Offset 0X4404)-BCM5722, BCM5755, BCM5755M, BCM5756M
365
MBUF Pool Base Address Register (Offset 0X4408)
366
MBUF Pool Length Register (Offset 0X440C)
366
Read DMA MBUF Low Watermark Register (Offset 0X4410)
366
Table 300: MBUF Pool Base Address Register (Offset 0X4408)
366
Table 301: MBUF Pool Length Register (Offset 0X440C)
366
MAC RX MBUF Low Watermark Register (Offset 0X4414)
367
MBUF High Watermark Register (Offset 0X4418)
367
RX RISC MBUF Cluster Allocation Request Register (Offset 0X441C)
367
Table 302: RX RISC MBUF Allocation Request Register (Offset 0X441C)
367
BM Hardware Diagnostic 1 Register (Offset 0X444C)
368
BM Hardware Diagnostic 2 Register (Offset 0X4450)
368
RX RISC MBUF Allocation Response Register (Offset 0X4420)
368
Table 303: BM Hardware Diagnostic 1 Register (Offset 0X444C)
368
Table 304: BM Hardware Diagnostic 2 Register (Offset 0X4450)
368
BM Hardware Diagnostic 3 Register (Offset 0X4454)
369
Receive Flow Threshold Register (Offset 0X4458)
369
Table 305: BM Hardware Diagnostic 3 Register (Offset 0X4454)
369
Table 306: Receive Flow Threshold Register (Offset 0X4458)
369
Read DMA Control Registers
370
Read DMA Mode Register (Offset 0X4800)
370
Table 307: Read DMA Control Registers-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
370
Table 308: Read DMA Control Registers-BCM5906 Only
370
Table 309: Read DMA Mode Register (Offset 0X4800)
370
Read DMA Programmable Ipv6 Extension Header Register (Offset: 0X4808)
372
Read DMA Status Register (Offset 0X4804)
372
Table 310: Read DMA Status Register (Offset 0X4804)
372
Table 311: Read DMA Programmable Ipv6 Extension Header Register (Offset: 0X4808)
372
Table 312: Write DMA Control Registers
373
Table 313: Write DMA Mode Register (Offset 0X4C00)
373
Write DMA Control Registers
373
Write DMA Mode Register (Offset 0X4C00)
373
Write DMA Status Register (Offset 0X4C04)
374
RX RISC Mode Register (Offset 0X5000)
376
RX RISC Registers
376
Table 315: RX RISC Registers
376
Table 316: RX RISC Mode Register Fields (Offset 0X5000)
376
RX RISC State Register (Offset 0X5004)
377
Table 317: RX RISC State Fields (Offset 0X5004)
377
RX RISC Hardware Breakpoint Register (Offset 0X5034)
379
RX RISC Program Counter (Offset 0X501C)
379
Table 318: RX RISC Hardware Breakpoint Register (Offset 0X5034)
379
Table 319: Virtual CPU Registers
380
Table 320: VCPU Status Register Fields (Offset 0X5100)
380
VCPU Status Register (Offset 0X5100)
380
Virtual CPU Registers (BCM5906 Only)
380
Device Configuration Shadow Register (Offset 0X5104)
381
Table 321: VCPU Status Register Fields (Offset 0X5100)
381
Table 322: RX RISC State Fields (Offset 0X5104)
381
Table 323: VCPU Holding Register (Offset 0X5108)
381
Table 324: VCPU Data Register (Offset 0X510C)
381
Virtual CPU Data Register (Offset 0X510C)
381
Virtual CPU Holding Register (Offset 0X5108)
381
Table 325: Virtual CPU Debug Register Fields (Offset 0X5110)
382
Table 326: Virtual CPU Debug Register Fields (Offset 0X5110)
382
Table 327: Virtual CPU Debug Register Fields (Offset 0X5110)
382
Virtual CPU Debug Register (Offset 0X5110)
382
Virtual CPU Shadow 1 Register (Offset 0X5114)
382
Virtual CPU Shadow 2 Register (Offset 0X5118)
382
BCM5754, BCM5787 Only
383
Low-Priority Mailboxes
383
Table 328: Low-Priority Mailbox Registers-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757
383
Table 329: Low-Priority Mailbox Registers-BCM5906 Only
383
Interrupt Mailbox 0 Register (Offset 0X5800-0X5807)
384
ISO Send BD Ring Host Producer Indices Registers (Offset 0X5908-0X590F)
384
Receive BD Return Ring 1 Consumer Index Register (Offset 0X5880-0X5887)
384
Receive BD Return Ring 2 Consumer Index Register (Offset 0X5888-0X588F)
384
Receive BD Return Ring 2 Consumer Index Register (Offset 0X5898-0X589F)
384
Receive BD Return Ring 3 Consumer Index Register (Offset 0X5890-0X5897)
384
Receive BD Standard Producer Ring Index Register (Offset 0X5868-0X586F)
384
Send BD Ring Host Producer Indices Registers (Offset 0X5900-0X5907)
384
Flow-Through Queues
385
FTQ Reset Register (Offset 0X5C00)
385
Table 330: Flow-Through Queues Registers
385
Table 331: FTQ Reset Register (Offset 0X5C00)
385
MAC TX FIFO Enqueue Register (Offset 0X5Cb8)
386
Table 332: MAC TX FIFO Enqueue Register (Offset 0X5Cb8)
386
Table 333: RXMBUF Cluster Free Enqueue Register (Offset 0X5Cc8)
387
Table 334: RDIQ FTQ Write/Peek Register (Offset 0X5Cfc)
387
Table 335: Functional Truth Table for the Combination of the Valid, Skip, and Pass Bits
388
Table 336: Message Signaled Registers
389
Table 337: MSI Mode Register (Offset 0X6000)
389
Table 338: MSI Status Register (Offset 0X6004)
389
Table 339: MSI FIFO Access Register (Offset 0X6008)
390
Table 340: General Control Registers-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
391
Table 341: General Control Registers-BCM5906 Only
391
Table 342: Mode Control Register (Offset 0X6800)
392
Table 343: Miscellaneous Configuration Register (Offset 0X6804)
394
Table 344: Miscellaneous Local Control Register (Offset 0X6808)
395
Table 345: Timer Register (Offset 0X680C)
396
Table 346: RX-RISC Event Register (Offset 0X6810)-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
397
Table 347: RX-RISC Event Register (Offset 0X6810)-BCM5906 Only
398
Table 348: RX-RISC Timer Reference Register (Offset 0X6814)
399
Table 349: RX-RISC Semaphore Register (Offset 0X6818)
399
Table 350: Serial EEPROM Address Register (Offset 0X6838)
400
Table 351: Serial EEPROM Data Register (Offset 0X683C)
400
Table 352: Serial EEPROM Control Register (Offset 0X6840)
400
Table 353: MDI Control Register (Offset 0X6844)
401
Table 354: RX CPU Event Enable Register (Offset 0X684C)-BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
402
Table 355: RX CPU Event Enable Register (Offset 0X684C)-BCM5906 Only
403
Table 356: Wake-On-LAN Registers
404
Table 357: WOL Mode Register (Offset 0X6880)
404
Table 358: WOL Config Register (Offset 0X6884)
404
Table 359: WOL State Machine Status Register (Offset 0X6888)
405
BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757, BCM5754, BCM5787 Only
406
Table 360: Miscellaneous Cable Sense Control Register (Offset: 0X6890)
406
Table 361: Miscellaneous Cable Sense Control Register (Offset: 0X6890)-BCM5906 Only
406
Table 362: Fast Boot Program Counter Register (Offset 0X6894)
407
Table 363: Chip Mode Register (Offset: 0X6898)
408
Table 364: Energy Detect Timer Register (Offset: 0X689C)
409
Table 365: Miscellaneous Clock Control Register (Offset: 0X68A0)
410
Table 366: Power Management Debug Register (Offset: 0X68A4)
411
Table 367: Energy_Det Control Register (Offset: 0X68B0)
412
Table 368: ASF Support Registers
414
Table 369: ASF Control Register (Offset 0X6C00)
415
Table 370: Smbus Input Register (Offset 0X6C04)
416
Table 371: Smbus Output Register (Offset 0X6C08)
417
Table 372: ASF Watchdog Timer Register (Offset 0X6C0C)
418
Table 373: ASF Heartbeat Timer Register (Offset 0X6C10)
418
Table 374: Poll ASF Timer Register (Offset 0X6C14)
419
Table 375: Poll Legacy Timer Register (Offset 0X6C18)
419
Table 376: Retransmission Timer Register (Offset 0X6C1C)
419
Table 377: Time Stamp Counter Register (Offset 0X6C20)
419
Table 378: Smbus Driver Select Register (Offset 0X6C24)
420
Table 379: ASF RNG Command Register (0X6C30)
420
Table 380: ASF RNG Data Register (0X6C34)
420
Table 381: Auxiliary Smbus Master Status Register (Offset 0X6C40)
421
Table 382: Auxiliary Smbus Master Control Register (Offset 0X6C44)
422
Table 383: Auxiliary Smbus Master Command Register (Offset 0X6C48)
423
Table 384: Auxiliary Smbus Block Data Register (Offset 0X6C4C)
423
Table 385: Auxiliary Smbus Slave Address/Control Register (Offset 0X6C50)
424
Table 386: Auxiliary Smbus Slave Status Register (Offset 0X6C54)
424
Table 387: Auxiliary Smbus Slave Data Register (Offset 0X6C58)
425
Table 388: Smbus ARP Command Register (Offset 0X6C60)
425
Table 389: Smbus ARP Status Register (Offset 0X6C64)
426
Table 390: UDID Register 0 (Offset 0X6C68)
426
Table 391: UDID Register 1 (Offset 0X6C6C)
427
Table 392: UDID Register 2 (Offset 0X6C70)
427
Table 393: UDID Register 3 (Offset 0X6C74)
427
Table 394: Non-Volatile Memory Interface Registers
428
Table 395: NVM Command Register (Offset 0X7000)
429
Table 396: NVM Status Register (0X7004H)
429
Table 397: NVM Write Register (Offset 0X7008)
430
Table 398: NVM Address Register (Offset 0X700C)
430
Table 399: NVM Read Register (Offset 0X7010)
430
Table 400: NVM Config 1 Register (Offset 0X7014)
431
Table 401: NVM Config 2 Register (Offset 0X7018)
432
Table 402: NVM Config 3 Register (Offset 0X701C)
433
Table 403: Software Arbitration Register (Offset 0X7020)
433
Table 404: NVM Access Register (Offset 0X7024)
434
Table 405: NVM Write1 Register (Offset 0X7028)
435
Table 406: NVM Arbitration Watchdog Timer Register (Offset 0X702C)
435
Table 407: NVM Auto-Sense Status Register (0X7038H)
436
Table 408: bist Registers
437
Table 409: bist Control Register (Offset 0X7400)
437
Table 410: bist Status Register (Offset 0X7404)
437
Table 411: bist Status Register (Offset 0X7404)
438
Table 412: Pcie Registers
440
Table 413: TLP Control Register (Offset 0X7C00)
442
Table 414: Transaction Configuration Register (0X7C04)
443
Table 415: Write DMA Request Upper Address Diagnostic Register (Offset 0X7C10)
446
Table 416: Write DMA Request Lower Address Diagnostic Register (Offset 0X7C14)
446
Table 417: Write DMA Length/Byte Enable and Request Diagnostic Register (Offset 0X7C18)
447
Table 418: Read DMA Request Upper Address Diagnostic Register (Offset 0X7C1C)
447
Table 419: Read DMA Request Lower Address Diagnostic Register (Offset 0X7C20)
447
Table 420: Read DMA Length and Request Diagnostic Register (Offset 0X7C24)
447
Table 421: MSI DMA Request Upper Address Diagnostic Register (Offset 0X7C28)
448
Table 422: MSI DMA Request Lower Address Diagnostic Register (Offset 0X7C2C)
448
Table 423: MSI DMA Length and Request Diagnostic Register (Offset 0X7C30)
448
Table 424: Slave Request Length and Type Diagnostic Register (Offset 0X7C34)
449
Table 425: Flow Control Inputs Diagnostic Register (Offset 0X7C38)
449
Table 426: XMT State Machines and Gated Requests Diagnostic Register (Offset 0X7C3C)
450
Table 427: Address ACK Xfer Count and ARB Length Diagnostic Register (Offset 0X7C40)
450
Table 428: DMA Completion Header Diagnostic Register 0 (Offset 0X7C44)
450
Table 429: DMA Completion Header Diagnostic Register 1 (Offset 0X7C48)
451
Table 430: DMA Completion Header Diagnostic Register 2 (Offset 0X7C4C)
451
Table 431: DMA Completion Misc. Diagnostic Register (Offset 0X7C50)
451
0X7C5C)
452
Table 432: DMA Completion Misc. Diagnostic Register (Offset 0X7C54)
452
Table 433: DMA Completion Misc. Diagnostic Register (Offset 0X7C58)
452
Table 434: Split Controller Requested Length and Address ACK Remaining Diagnostic Register
452
Table 435: Split Controller Misc 0 Register Diagnostic Register (Offset 0X7C60)
453
Table 436: Split Controller Misc 1 Register Diagnostic Register (Offset 0X7C64)
453
Table 437: TLP Status Register (Offset 0X7C60)
453
Table 438: TLP Status Register (Offset 0X7C60)
454
Table 439: Data Link Control Register (Offset 0X7D00)
454
Table 440: Data Link Status Register (Offset 0X7D04)
456
Table 441: Data Link Attention Register (Offset 0X7D08)
457
Table 442: Data Link Attention Mask Register (Offset 0X7D0C)
457
Table 443: Next Transmit Sequence Number Debug Register (Offset 0X7D10)
458
Table 444: Acked Transmit Sequence Number Debug Register (Offset 0X7D14)
458
Table 445: Purged Transmit Sequence Number Debug Register (Offset 0X7D18)
458
Table 446: Receive Sequence Number Debug Register (Offset 0X7D1C)
458
Table 447: Data Link Replay Register (Offset 0X7D20)
458
Table 448: Data Link ACK Timeout Register (Offset 0X7D24)
459
Table 449: Power Management Threshold Register (Offset 0X7D28)
459
Table 450: Retry Buffer Write Pointer Debug Register (Offset 0X7D2C)
459
Table 451: Retry Buffer Read Pointer Debug Register (Offset 0X7D30)
459
Table 452: Retry Buffer Purged Pointer Debug Register (Offset 0X7D34)
460
Table 453: Retry Buffer Read/Write Debug Port (Offset 0X7D38)
460
Table 454: Error Count Threshold Register (Offset 0X7D3C)
460
Table 455: TLP Error Counter Register (Offset 0X7D40)
460
Table 456: DLLP Error Counter (Offset 0X7D44)
461
Table 457: NAK Received Counter (Offset 0X7D48)
461
Table 458: Data Link Test Register (Offset 0X7D4C)
461
Table 459: Packet bist Register (Offset 0X7D50)
462
Table 460: Link Pcie 1.1 Control Register (0X7D54)
463
Table 461: PHY Mode Register (Offset 0X7E00)
464
Table 462: Phy/Link Status Register (Offset 0X7E04)
464
Table 463: Phy/Link LTSSM Control Register (Offset 0X7E08)
465
Table 464: Phy/Link Training Link Number (Offset 0X7E0C)
465
Table 465: Phy/Link Training Lane Number (Offset 0X7E10)
465
Table 466: Phy/Link Training N_FTS (Offset 0X7E14)
466
Table 467: PHY Attention Register (Offset 0X7E18)
466
Table 468: PHY Attention Mask Register (Offset 0X7E1C)
467
Table 469: PHY Receive Error Counter (Offset 0X7E20)
467
Table 470: PHY Receive Framing Error Counter (Offset 0X7E24)
467
Table 471: PHY Receive Error Threshold Register (Offset 0X7E28)
468
Table 472: PHY Test Control Register (Offset 0X7E2C)
468
Table 473: Phy/Serdes Control Override Register (Offset 0X7E30)
470
Table 474: PHY Timing Parameter Override Register (Offset 0X7E34)
471
Table 475: PHY Hardware Diagnostic 1 Register (Offset 0X7E38)
471
Table 476: PHY Hardware Diagnostic 2 Register (Offset 0X7E3C)
472
Table 477: Transceiver Register Map
473
Table 478: MII Control Register (Phy_Addr = 0X1, Reg_Addr = 00H)
474
Table 479: MII Status Register (Phy_Addr = 0X1, Reg_Addr = 01H)
475
Table 480: PHY Identifier Registers (Phy_Addr = 0X1, Reg_Address 02H)
477
Table 481: PHY Identifier Registers (Phy_Addr = 0X1, Reg_Address 03H)
477
Table 482: Auto-Negotiation Advertisement Register (Phy_Addr = 0X1, Reg_Addr = 04H)
478
Table 483: Auto-Negotiation Link Partner Ability Register (Phy_Addr = 0X1, Reg_Addr = 05H)
480
Table 484: Auto-Negotiation Expansion Register (Phy_Addr = 0X1, Reg_Addr = 06H)
481
Table 485: Next Page Transmit Register (Phy_Addr = 0X1, Reg_Addr = 07H)
482
Table 486: Link Partner Received Next Page Register (Phy_Addr = 0X1, Reg_Addr = 08H)
483
Table 487: 1000BASE-T Control Register (Phy_Addr = 0X1, Reg_Addr = 09H)
484
Table 488: 1000BASE-T Status Register (Phy_Addr = 0X1, Reg_Addr = 0Ah)
485
Table 489: IEEE Extended Status Register (Phy_Addr = 0X1, Reg_Addr = 0Fh)
486
Table 490: PHY Extended Control Register (Phy_Addr = 0X1, Reg_Addr = 10H)
487
Table 491: PHY Extended Status Register (Phy_Addr = 0X1, Reg_Addr = 11H)
489
Table 492: Receive Error Counter (Phy_Addr = 0X1, Reg_Addr = 12H)
491
Table 493: False Carrier Sense Counter (Phy_Addr = 0X1, Reg_Addr = 13H)
491
Table 494: Receiver NOT_OK Counters (Phy_Addr = 0X1, Reg_Addr = 14H, Normal Operation)
492
Table 495: Receiver NOT_OK Counters (Phy_Addr = 0X1, Reg_Addr = 14H, CRC Error Count Operation)
492
Table 496: Expansion Register Access Register (PHY_ADDR = 0X1, Reg_Addr = 17H)
493
Table 497: Expansion Register Select Values
493
Table 498: Expansion Register 00H: Receive/Transmit Packet Counter
494
Table 499: Expansion Register 01H: Expansion Interrupt Status
494
Table 500: Expansion Register 03H: Serdes Control
495
Table 501: Expansion Register 04H: Multicolor LED Selector
496
Table 502: Expansion Register 05H: Multicolor LED Flash Rate Controls
497
Table 503: Expansion Register 06H: Multicolor LED Programmable Blink Controls
498
Table 504: Expansion Register 10H: Cable Diagnostic Controls
499
Table 505: Expansion Register 11H: Cable Diagnostic Results
500
Table 506: Expansion Register 12H: Cable Diagnostic Lengths Channels1/2
501
Table 507: Expansion Register 13H: Cable Diagnostic Lengths Channels 3/4
502
Table 508: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 000, Normal)
503
Table 509: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 001, 10BASE-T)
505
Power Control)
506
Table 511: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 100, Misc Test 1)
507
Table 512: Auxiliary Control Register (Phy_Addr = 0X1, Reg_Addr = 18H, Shadow = 111, Misc Control)
508
Table 513: Auxiliary Status Summary Register (Phy_Addr = 0X1, Reg_Addr = 19H)
509
Table 514: Interrupt Status Register (Phy_Addr = 0X1, Reg_Addr = 1Ah)
512
Table 515: Interrupt Mask Register (Phy_Addr = 0X1, Reg_Addr = 1Bh)
514
Table 516: Spare Control 1 Register (Address 1Ch, Shadow Value 00010)
514
Table 517: Clock Alignment Control Register (Address 1Ch, Shadow Value 00011)
515
Table 518: Spare Control 2 Register (Address 1Ch, Shadow Value 00100)
516
Table 519: Spare Control 3 Register (Address 1Ch, Shadow Value 00101)
517
Table 520: LED Status Register (Address 1Ch, Shadow Value 01000)
518
Table 521: LED Control Register (Address 1Ch, Shadow Value 01001)
520
Table 522: Auto Power down Register (Address 1Ch, Shadow Value 01010)
521
Table 523: LED Selector 1 Register (Address 1Ch, Shadow Value 01101)
522
Table 524: LED Selector 2 Register (Address 1Ch, Shadow Value 01110)
524
Table 525: LED GPIO Control/Status Register (Address 1Ch, Shadow Value 01111)
525
Table 526: Autodetect Sgmii/Media Converter Register (Address 1Ch, Shadow Value 11000)
526
Table 527: 1000BASE-X Auto-Negotiation Debug Register (Address 1Ch, Shadow Value 11010)
527
Table 528: Auxiliary 1000BASE-X Control Register (Address 1Ch, Shadow Value 11011)
529
Table 529: Auxiliary 1000BASE-X Status Register (Address 1Ch, Shadow Value 11100)
530
Table 530: Misc 1000BASE-X Status Register (Address 1Ch, Shadow Value 11101)
532
Table 531: Autodetect Medium Register (Address 1Ch, Shadow Value 11110)
534
Table 532: Mode Control Register (Address 1Ch, Shadow Value 11111)
536
Table 533: HCD Status Register (Phy_Addr = 0X1, Reg_Addr = 1Dh, Bit 15 = 1)
538
Table 534: Master/Slave Seed Register (Phy_Addr = 0X1, Reg_Addr = 1Dh, Bit 15 = 0)
539
Table 535: PHY Test Register 1 (Phy_Addr = 0X1, Reg_Addr = 1Eh)
539
Table 536: MII Management Frame Format
540
Table 537: MII Register Summary
541
Table 538: Control Register (Address 00D, 00H)
543
Table 539: MII Status Register (Address 01D, 01H)
545
Table 540: PHY Identifier Registers (Addresses 02D and 03D, 02H and 03H)
546
Table 541: Auto-Negotiation Advertisement Register (Address 04D, 04H)
547
Table 542: Auto-Negotiation Link Partner Ability Register (Address 05D, 05H)
548
Table 543: Auto-Negotiation Expansion Register (Address 06D, 06H)
549
Table 544: Next Page Transmit Register (Address 07D, 07H)
550
Table 545: Next Page Transmit Register (Address 08D, 08H)
551
Table 546: 100-BASE-X Auxiliary Control Register (Address 16D, 10H)
552
Table 547: 100BASE-X Auxiliary Status Register (Address 17D, 11H)
553
Table 548: 100BASE-X Receive Error Counter (Address 18D, 12H)
554
Table 549: 100BASE-X False Carrier Sense Counter (Address 19D, 13H)
555
Table 550: 100BASE-X Disconnect Counter (Address 20D, 14H)
555
Table 551: Auxiliary Control/Status Register (Address 24D, 18H)
556
Table 552: Auxiliary Status Summary Register (Address 25D, 19H)
558
Table 553: Interrupt Register (Address 26D, 1Ah)
559
Table 554: Auxiliary Mode 2 Register (Address 27D, 1Bh)
561
Table 555: 10BASE-T Auxiliary Error and General Status Register (Address 28D, 1Ch)
563
Table 556: Auxiliary Mode Register (Address 29D, 1Dh)
565
Table 557: Auxiliary Multiple PHY Register (Address 30D, 1Eh)
566
Table 558: Broadcom Test Register (Address 31D, 1Fh)
567
Table 559: Miscellaneous Control Register (Shadow Register 16D, 10H)
568
Table 560: Auxiliary Status 2 Register (Shadow Register 27D, 1Bh)
568
Table 561: 100-TX Port Cable Length
569
Table 562: Auxiliary Status 3 Register (Shadow Register 28D, 1Ch)
570
Table 563: Auxiliary Mode 3 Register (Shadow Register 29D, 1Dh)
571
Table 564: Current Receive FIFO Size
571
Table 565: Auxiliary Status 4 Register (Shadow Register 30D, 1Eh)
571
Figure 68: File Transfer Scenario: FTP Session Begins
573
Figure 69: File Transfer Scenario: Speed Mismatch
573
Figure 70: File Transfer Scenario: Speed Buffers Run Low
574
Figure 71: File Transfer Scenario: Switch Backpressure
575
Figure 72: File Transfer Scenario: Switch Flow Control
575
Figure 73: File Transfer Scenario: File Transfer Complete
576
Figure 74: Pause Control Frame
576
Figure 75: APM Architecture
578
Figure 76: States for Power Consumption Management
579
Table 566: Function Codes Quick Reference
579
Table 567: Event Codes Quick Reference
580
Figure 77: Advanced Configuration and Power Interface (ACPI) Components
582
Figure 78: os Power Management (OSPM) Global States
583
Figure 79: ACPI Sleep States
584
Table 568: Power Management Behavior for the Network Device Class
585
Table 569: Power Management Policy for the Network Class
585
Figure 80: Power Management Configuration During POST
587
Figure 81: General Purpose Event Block
588
Figure 82: PCI-Specified Reset Interval
589
Figure 83: GPIO Hold Condition
590
Table 570: Terminology
591
Advertisement
Advertisement
Related Products
Broadcom BCM5722
Broadcom NetXtreme/NetLink BCM5720
Broadcom BCM5708C
Broadcom BCM5706C
Broadcom BCM5706S
Broadcom NetXtreme BCM57 Series
Broadcom NetXtreme/NetLink BCM5717
Broadcom NetXtreme/NetLink BCM5719
Broadcom NetXtreme BCM57XX
Broadcom NetXtreme BCM570 Series
Broadcom Categories
PCI Card
Motherboard
Adapter
Controller
Computer Hardware
More Broadcom Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL