Table 355: Rx Cpu Event Enable Register (Offset 0X684C)-Bcm5906 Only - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
Table 355: RX CPU Event Enable Register (Offset 0x684C)—BCM5906 Only
Bit Field
31 Flash
30 VPD
29 Reserved
28 ROM
27 HC module
26 Reserved
25 EMAC module
24 Memory Map Enable Bit
23 Reserved -
22 Reserved -
21 Low-Priority Mail Box -
20 DMA -
19 Reserved -
18 Datalink Layer -
17 Physical Layer
16:11 Reserved -
10 SDC (Post TCP
segmentation) -
9 SDI (Pre TCP segmentation)
-
8 RDIQ FTQ
7:0 Reserved
Document 5722-PG101-R
Description
–
–
–
–
–
–
–
Set by HW, cleared by SW
–
–
–
–
–
–
–
–
–
–
–
–
Bro adco m Co rp or atio n
BCM5722
Init Access
0 RO
0 RO
0 R/W
0 RO
0 RO
0 RO
0 RO
0 R/W
0 R/W
0 RO
0 RO
0 RO
0 R/W
00 R/W
0 R/W
0 RO
0 RO
0 RO
0 R/W
General Control Registers Page 344