Table 356: Wake-On-Lan Registers; Table 357: Wol Mode Register (Offset 0X6880); Table 358: Wol Config Register (Offset 0X6884) - Broadcom BCM5722 Programmer's Manual

BCM5722
W - -LAN R
AKE ON
Note: The Wake-on-LAN registers do not apply to the BCM5906 device.
Field
0x6880–0x6883
0x6884–0x6887
0x6888–0x688B
0x688C–0x688F
WOL M R
ODE EGISTER
Bit Field
31:5 Reserved
4 WOL_PWR_CTRL
3:2 WOL_PWR_SW_PRO
G
1 Enable
0 Reset
WOL C R
ONFIG EGISTER
Bit Field
31:17 Reserved
16 SC_sim_mode
15:14 SC_delay_cfg
13 SD_sim_mode
Page 345 Wake-on-LAN Registers
EGISTERS

Table 356: Wake-on-LAN Registers

Description
WOL Mode Register
WOL Config Register
WOL State Machine Status Register
Reserved
(O 0 6880)
FFSET X

Table 357: WOL Mode Register (Offset 0x6880)

Description
–
Use to manually switch the power FETs.
Control the WOL voltage comparator threshold (100 mV
increment).
This bit controls whether the WOL is active or not.
• When set to 0, it completes the current operation and
cleanly halts.
• Until it is completely halted, it remains one when read.
When set, the entire WOL state machines are reset. This
bit is self-clearing.
(O 0 6884)
FFSET X

Table 358: WOL Config Register (Offset 0x6884)

Description
When set to 1, it indicates the main power is available.
When set to 1, it accelerate the simulations. It waits only
0.5 µs. When set to 0, it is normal operation.
When set to 00, it accelerates the simulations for
slow_clock_ctl.
• 00 = waits 10 µs.
• 01 = waits 35 µs.
• 10 = waits 50 µs.
• 11 = waits 65 µs.
• 0 = normal operation mode. The total delay is
SD_delay_cfg x1000.
• 1 = waits 0.5 µs.
Bro adco m C orp or atio n
Programmer's Guide
10/15/07
Init Access
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Init Access
0 R/W
0 R/W
0 R/W
0 R/W
Document 5722-PG101-R