Programmer's Guide
10/15/07
1000BASE-X A
UTO
11010
)
B
Table 527: 1000BASE-X Auto-Negotiation Debug Register (Address 1Ch, Shadow Value 11010)
Bit
Field
15
Write Enable
14:10
Shadow Register Selector
9
Consistency Mismatch
8
RUDI Invalid
7
Comma Detected
6
AN_Sync_Status
5
Idle Detect State
4
Complete Acknowledge
State
3
Acknowledge Detect State • 1 = Acknowledge detect state entered since last read.
2
Ability Detect State
1
Error State
0
AN_Enable State
Write Enable
During a write to this register, setting LED 1000BASE-X Auto-negotiation Debug register bit 15 to a 1 allows writing to bits
[7:0] of this register. For reading the values of bits [9:0], perform an MDIO write with bit 15 set to a 0 and preferred shadow
values in bits [14:10]. The next MDIO read of register address 1Ch contains the preferred shadow register values in bits [9:0].
Shadow Register Selector
Bits [14:10] of this register must be set to 11010 to enable read/write to the 1000BASE-X Auto-negotiation Debug register.
Consistency Mismatch
Bit 9 of 1000BASE-X Auto-negotiation Debug register indicates a consistency mismatch occurred since last read.
RUDI Invalid
Bit 8 of 1000BASE-X Auto-negotiation Debug register indicates a RUDI (Rx_UnitData Indicate, specified in IEEE 36.2.5.1.6)
invalid detected since last read.
Document
5722-PG101-R
-N
D
EGOTIATION
EBUG
Description
• 1 = Write bits [9:0].
• 0 = Read bits [9:0].
11010 = 1000BASE-X Auto-negotiation Debug register.
• 1 = Consistency mismatch occurred since last read.
• 0 = No consistency mismatch occurred since last read.
• 1 = RUDI invalid detected since last read.
• 0 = No RUDI invalid detected since last read.
• 1 = Comma detected since last read.
• 0 = No comma detected since last read.
• 1 = AN_sync_status has not failed since last read.
• 0 = AN_sync_status failed since last read.
• 1 = Idle detect state entered since last read.
• 0 = Idle detect state has not been entered since last read.
• 1 = Complete acknowledge state entered since last read.
• 0 = Complete acknowledge state has not been entered since
last read.
• 0 = Acknowledge detect state has not been entered since last
read.
• 1 = Ability detect state entered since last read.
• 0 = Ability detect state has not been entered since last read.
• 1 = Error state entered since last read.
• 0 = Error state has not been entered since last read.
• 1 = AN_enable state entered since last read.
• 0 = AN_enable state has not been entered since last read.
Bro adco m Co rp or atio n
(PHY_A
= 0
1, R
DDR
X
BCM5722
_A
= 1C
, S
EG
DDR
H
Init
0
11010
0
0
0
0
0
0
0
0
0
0
Transceiver Registers
HADOW
Access
R/W
R/W
RO
LH
RO
LH
RO
LH
RO
LH
RO
LH
RO
LH
RO
LH
RO
LH
RO
LH
RO
LH
Page 468
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