Table 471: Phy Receive Error Threshold Register (Offset 0X7E28); Table 472: Phy Test Control Register (Offset 0X7E2C) - Broadcom BCM5722 Programmer's Manual

BCM5722
PHY R E
ECEIVE RROR

Table 471: PHY Receive Error Threshold Register (Offset 0x7E28)

Bit Field
31:12 Reserved
11:8 Frame Error
Threshold
7:4 Disparity Error
Threshold
3:0 Code Error
Threshold
PHY T C
EST ONTROL
Bit Field
31:23 Reserved
22 Two OS rule relaxing
(BCM5787,
BCM5787M,
BCM5754, BCM5754M
devices only)
Reserved (other
devices)
20 Disable Link Down
Reset (BCM5787,
BCM5787M,
BCM5754, BCM5754M
devices only)
Reserved (other
devices)
18 Disable Error Exit
(BCM5787,
BCM5787M,
BCM5754, BCM5754M
devices only)
Reserved (other
devices)
Page 409 PCIe Registers
T R
HRESHOLD EGISTER
Description
–
Receive frame error threshold. When the frame
error count exceeds this threshold. The frame
error attention bit is set. Threshold=2^n, where
n=bits(11:8).
Receive 8b10b running disparity error
threshold. When the running disparity error
count exceed this threshold, the disparity error
will be set. Threshold = 2^n, where n = bits(7:4).
Receive 8b10b coding error threshold. When
the code error count exceeds threshold, the
code error attention bit is set. Threshold = 2^n,
where n = bits(3:0).
R (O
EGISTER FFSET

Table 472: PHY Test Control Register (Offset 0x7E2C)

Description
–
• 1 = Relax two consecutive ordered set rule checking. The
OS count continues with alternating TS1 and TS2
• 0 = Strictly consecutive ordered set rule checking.The OS
count continues only with the same type of OS, not with
alternating TS1 and TS2
• 1 = To cause link down reset to LTSSM when detect link
down event.
• 0 = To not cause link down reset to LTSSM at link down
event. The link down reset will be propagated to the rest of
the chip, except the LTSSM.
• 1 = To continue receiving a frame when detect a symbol
error, until a frame delimiter is received.
• 0 = To exit receiving a frame when detect a symbol error.
Bro adco m C orp or atio n
(O 0 7E28)
FFSET X
Init
0
0x4 (For BCM5787, BCM5787M,
BCM5754, and BCM5754M only)
0xF (For BCM5722, BCM5755,
BCM5755M, BCM5756M, BCM5757
only)
0x4 (For BCM5787, BCM5787M,
BCM5754, and BCM5754M only)
0xF (For BCM5722, BCM5755,
BCM5755M, BCM5756M, BCM5757
only)
0x4 (For BCM5787, BCM5787M,
BCM5754, and BCM5754M only)
0xF (For BCM5722, BCM5755,
BCM5755M, BCM5756M, BCM5757
only)
0 7E2C)
X
Programmer's Guide
10/15/07
Access
RO
R/W
R/W
R/W
Init Access
0 RO
0 RW
0 RO
0 RW
0 RO
0 RW
0 RO
Document 5722-PG101-R