Broadcom BCM5722 Programmer's Manual page 87

Programmer's Guide
10/15/07
O
VERVIEW
The System Management block of the NetXtreme devices contains all of the hardware necessary to support a
implementation of the ASF protocol primarily in firmware. This hardware includes six dedicated timers, a low-level
SMBus 2.0-compliant interface, registers for driving the SMBus interface, and a global control and event register. The
system management block can also be used to support additional (non-ASF) management technologies such as IPMI.
T
IMERS
The System Management block contains five countdown timers that stop when they reach zero and one free-running
timestamp counter. The countdown timers all have a corresponding event bit in the control and event register. The event bit
is set when the counters transition from a value of one to a value of zero. The timestamp counter starts when its enable bit
is set in the control register and rolls over when it reaches its maximum value.
SMB I
US NTERFACE
The SMBus interface provides a serial interface for byte-wide words and allows the firmware to directly control the operation
of the bus. The SMB Enable bit (bit 12) in the ASF Control register (see
enables the interface.
The interface is capable of master and slave modes of operation. A master operation is initiated by writing the first byte of
data to the SMB Output register (see
RDY bit, and any other desired control bits for that transaction. Subsequent data bytes to be transmitted are then written to
the same register with the RDY bit set. For the last transmit byte, the LAST bit and RDY bit are set. The transmit bytes are
transferred from the SMB Output register to an internal FIFO whenever there is space, and the RDY bit is cleared when this
transfer takes place. Therefore, the RDY bit is used to determine if there is space to write the next transmit byte. The START
bit is cleared by the hardware when the transmit portion of the transfer is finished. At the same time, the status of the transmit
portion of the transfer is provided in the STATUS field.
The transmit portion of the transfer could end at any time due to arbitration loss, no-ACK from the target, or assorted error
conditions. If the transfer is a read transaction, then the read data can now be retrieved from the SMB Input register. The
data field of this register is valid when the RDY bit is set. The input portion of the SMBus interface also has a small internal
FIFO, and data is transferred from this FIFO to the SMB Input register (see
page 357) automatically whenever the RDY bit is clear. If the SMB AUTOREAD bit (bit 15) of the ASF Control register is set,
then the RDY bit is cleared whenever the SMB Input register is read, thus allowing the next data byte to be loaded. The SMB
Input register has a DONE bit that is set when the receive portion of the transfer is completed. A status field is also provided
when the DONE bit is set. The DONE bit must be cleared by firmware after the status is retrieved. Also, the firmware must
flush all of the data out of the FIFO.
A slave mode operation starts whenever the SMBus interface detects activity on the bus, or if a master operation loses
arbitration during the first byte of the transfer. The interface does address filtering on the incoming data by looking at the first
byte of the transfer (if the SMB ADDR Filter bit is set in the ASF Control register). The address is compared to two different
fields in the ASF Control register, and to the value 0x00 if the SMB Enable ADDR Zero bit is set. If an address match is found,
then the interface acknowledges the incoming byte, and transfers the byte to the input FIFO. The RDY and DONE bits in the
SMB Input register behave in this mode basically the same as with master reads. If the slave access calls for read data, then
the firmware would send data to the interface via the SMB Output register in a manner similar to master-write accesses.
A bit-bang mode for this interface is also provided. To enable this mode, set the SMB Bit Bang Enable bit in the ASF Control
register and clear the SMB Enable bit. Control of the bus is accomplished by directly manipulating the SMB Bit Bang bits in
the SMB Output register as defined in the register definition.
Document 5722-PG101-R
"SMBus Output Register (Offset 0x6C08)" on page
Bro adco m Co rp or atio n
"ASF Control Register (Offset 0x6C00)" on page
358), along with a START bit, a
"SMBus Input Register (Offset 0x6C04)" on
System Management Bus
BCM5722
356)
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