Table 148: Link Control Register (Offset 0Xe0); Table 149: Link Status Command Register (Offset 0Xe2) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
L C R
INK ONTROL EGISTER
Bit Field
15:9 Reserved
8 clkreq enable
7 Extended Synch
6 Common Clock
Configuration
5:4 Reserved
3 Read Completion
Boundary
2 Reserved
1:0 Active State Power
Management Control
a. RO when bit 18 of register 0xDC is "0". R/W when bit 18 of register 0xDC is "1" for BCM5906/BCM5906M A2 and after only.)
L S C
INK TATUS OMMAND
Bit Field
15:13 Reserved
12 Slot Clock
Configuration
11:10 Reserved
9:4 Negotiated Link Width This value returns the negotiated link width. The only valid values are 1,
3:0 Link Speed
Document 5722-PG101-R
(O 0 E0)
FFSET X

Table 148: Link Control Register (Offset 0xE0)

Description
–
• 1 = Enable clkreq
• 0 = Disable clkreq
When this bit is set, it forces extended sync which gives external devices
(such as logic analyzers) additional time to achieve bit and symbol lock.
When this bit is set, it indicates that the link partners are using a common
reference clock.
–
This value indicates the Read Completion Boundary value (in bytes) of
the upstream root port.
• 0 = 64
• 1 = 128
–
This value controls the Active State Power Management supported on
this link.
• 0 = Disabled
• 1 = L0s Entry Enabled
• 2 = L1 Entry Enabled
• 3 = L0s and L1 Entry Enabled
R (O
EGISTER FFSET

Table 149: Link Status Command Register (Offset 0xE2)

Description
–
This value indicates that this device uses the same physical reference
clock that the platform provides on the connector.
–
2, 4, 8, 12, 16, and 32.
This value returns the negotiated link speed. 1 = 2.5 Gbps.
Bro adco m Co rp or atio n
0 E2)
X
BCM5722
Init Access
0 RO
0 RO,
a
R/W
0 R/W
0 R/W
0 RO
0 R/W
0 RO
0 R/W
Init Access
0 RO
RO
0 RO
1 RO
1 RO
PCIe Capabilities Page 220