Table 534: Master/Slave Seed Register (Phy_Addr = 0X1, Reg_Addr = 1Dh, Bit 15 = 0); Table 535: Phy Test Register 1 (Phy_Addr = 0X1, Reg_Addr = 1Eh) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
M /S S
ASTER LAVE EED

Table 534: Master/Slave Seed Register (PHY_Addr = 0x1, Reg_Addr = 1Dh, Bit 15 = 0)

Bit Field
15 Enable Shadow
Register
14 Master/Slave Speed
Match
13 Link partner Repeater/
DTE Bit
12 Link Partner Manual M/
S Config Value
11 Link Partner Manual M/
S Config Enable
10:0 Local Master/Slave
Seed Value
PHY T R
EST EGISTER

Table 535: PHY Test Register 1 (PHY_Addr = 0x1, Reg_Addr = 1Eh)

Bit Field
15 CRC Error Count
Visibility
14:8 Reserved
7 Manual Swap MDI
State
6:0 Reserved
Document 5722-PG101-R
R (PHY_A
EGISTER
Description
• 1 = Select Shadow register.
• 0 = Normal operation.
• 1 = Seeds match.
• 0 = Seeds don't match.
• 1 = Link partner is a repeater/switch device port.
• 0 = Link partner is a DTE device port.
• 1 = Link partner is configured as master.
• 0 = Link partner is configured as slave.
• 1 = Link partner manual master/slave configuration
enabled.
• 0 = Link partner manual master/slave configuration
disabled.
Returns the automatically generated Master/Slave
random seed.
1 (PHY_A = 0X1, REG_A
DDR
Description
• 1 = Receiver NOT_OK counters (see
NOT_OK Counters (PHY_Addr = 0x1, Reg_Addr =
14h)" on page
counter.
• 0 = Normal operation.
• 1 = Manual swap MDI state.
• 0 = Normal operation.
Write as 0, Ignore when read.
Bro adco m Co rp or atio n
= 0 1, R _A
DDR X EG
= 1EH)
DDR
"Receiver
433) merged into one 16-bit CRC error
= 1D , B 15 = 0)
DDR H IT
Init
0
0
0
0
0
000h
Init
0
0
0
0
Transceiver Registers
BCM5722
Access
R/W
RO, LH
RO
RO
RO
R/W
Access
R/W
R/W
R/W
R/W
Page 480