Table 344: Miscellaneous Local Control Register (Offset 0X6808) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
Table 343: Miscellaneous Configuration Register (Offset 0x6804) (Cont.)
Bit Field
16:13 Bond ID
12:8 Reserved
7:1 Timer Prescaler
Reserved (BCM5906 only)
0 CORE Clock Blocks Reset
a. PCIe configuration cycles are non-posted transactions and require a completion to avoid a PCIe bus error. Drivers using
configuration cycles to do a GRC reset on PCIe devices need to give the device enough time to send out the configuration
write completion before the PCIe link goes down. The driver should slow the clock down by setting bits 20 (not 19) and 12 in
register 0x74 before issuing configuration cycles for a GRC reset (bit 0 of register 0x6804) or setting the PWRDOWN bit
(0x6804 bit 20). This is not required if PCIe reset is disabled during the GRC reset by setting the bit 29 of this register (0x6804)
to 1.
M L
ISCELLANEOUS OCAL
The Miscellaneous Local Control register is used to control various functions within the device. All bits are set to zero (i.e.
disabled) during reset.
Bit Field
31 Enable Wolink Up
30 Enable Wolink Down
29 Disable Traffic LED Fix
(CQ9609)
28–27 Reserved
26 PME Assert (all other devices) When set, the PME Status bit in the PMSCR register (see
25 Reserved
24 Auto SEEPROM Access
23:17 Reserved
16:14 GPIO Pins [2:0] outputs
13:11 GPIO Pins [2:0] output
enables
10:8 GPIO Pins [2:0] inputs
7 Global Interrupt Enable
(BCM5787, BCM5787M,
BCM5754, and BCM5754M
only)
Reserved (other devices)
6 Reserved
Document 5722-PG101-R
Description
–
Local Core clock frequency in MHz, minus 1, which should
correspond to each advance of the timer. Reset to all 1.
Example: A 66-MHz local core clock uses 65 (0x41).
–
a
Write 1 to this bit resets the CORE_CLK blocks in the
device. This is a self-clearing bit.
C R
ONTROL EGISTER

Table 344: Miscellaneous Local Control Register (Offset 0x6808)

Description
When set, the chip drives the PME when the link is up.
When set, the chip drives the PME when the link is down.
Set to 1 to disable Traffic LED Fix
–
"PMCSR-BSE Register (Offset 0x4E)" on page
high. If PME Enable is also set, the PME signal will activate. This
register bit is write-only and self-clearing after write.
–
If set, access to serial EEPROM goes through the serial
EEPROM address and data registers. Otherwise, serial
EEPROM control register should be used.
–
Outputs which are defined by board level design.
When asserted, the device drives miscellaneous pin outputs.
Input from bidirectional miscellaneous pin.
When this bit is set, the interrupt to the CPU is enabled.
–
–
Bro adco m Co rp or atio n
(O 0 6808)
FFSET X
BCM5722
Init Access
ID(3:0) RO
00 RO
1111111 R/W
0 RO
0 R/W
Init Access
0 R/W
0 R/W
0 R/W
0 RO
0 RO
198) is forced
0 RO
0 R/W
0 RO
0 R/W
0 R/W
0 RO
0 R/W
0 RO
0 RO
General Control Registers Page 336