Table 141: Pcie Capability Id Register (Offset 0Xd0); Table 142: Pcie Next Capabilities Pointer Register (Offset 0Xd1); Table 143: Pcie Capabilities Register (Offset 0Xd2) - Broadcom BCM5722 Programmer's Manual

BCM5722
PCI C
E APABILITIES
PCIe devices include new status and control registers that are located in the Capabilities List in the device's PCI
Configuration Space. These PCIe capabilities registers start at offset 0xD0 of PCI Configuration Space.
PCI C L
E APABILITY IST
This eight-bit register identifies this item in the Capabilities List as a PCIe register set. This value is hardwired to 0x10 to
indicate the PCIe capabilities set.
Bit Field
7:0 PCIe Capability ID
PCI N C
E EXT APABILITIES
This eight-bit register points to the next item in the capabilities List.
Bit Field
7:0 PCIe Next Capabilities Points to the next capabilities block, which is NULL,
PCI C
E APABILITIES
Bit Field
15:14 Reserved
13:9 Interrupt Message
Number
8 Slot Implemented
7:4 Device/Port Type
3:0 Capability Version
a. Writable by internal processors.
Page 215 PCIe Capabilities
R (O
EGISTER FFSET

Table 141: PCIe Capability ID Register (Offset 0xD0)

Description
Identifies this item as PCIe capabilities.
P R
OINTER EGISTER

Table 142: PCIe Next Capabilities Pointer Register (Offset 0xD1)

Description
because this is the last item in the capabilities list.
R (O
EGISTER FFSET

Table 143: PCIe Capabilities Register (Offset 0xD2)

Description
–
This register contains the MSI Data value that is written to the MSI
destination address when any status bit in either the Slot Status
register or the Root Status register is set.
This register is hardwired to 0 because this is an endpoint device.
This register is hardwired to 0 because this is an endpoint device.
This register indicates the version of the PCIe Capability structure.
Bro adco m C orp or atio n
0 D0)
X
(O 0 D1)
FFSET X
0 D2)
X
Programmer's Guide
10/15/07
Init Access
10h RO
Init Access
00h RO
Init Access
0 R/W
a
0 R/W
0 RO
0 RO
1 RO
Document 5722-PG101-R