Table 385: Auxiliary Smbus Slave Address/Control Register (Offset 0X6C50); Table 386: Auxiliary Smbus Slave Status Register (Offset 0X6C54) - Broadcom BCM5722 Programmer's Manual

BCM5722
A SMB
UXILIARY US

Table 385: Auxiliary SMBus Slave Address/Control Register (Offset 0x6C50)

Bit Field
31:8 Reserved
7:1 SMBus Slave Address Only meaningful if AV flag is set. User also needs to
0 Slave Enable
A SMB
UXILIARY US

Table 386: Auxiliary SMBus Slave Status Register (Offset 0x6C54)

Bit Field
31:3 Reserved
2 Slave Read Requested • 0 = SMBus Attention not caused by slave.
1 Slave Cycle Complete • 0 = SMBus Attention not caused by slave.
0 Slave Busy
Page 365 ASF Support Registers
S A /C
LAVE DDRESS ONTROL
Description
–
program bit 0 of register 0x6C64 AV_REG to mark address
valid based on SMBus 2.0 spec.
• 0 = Disable
• 1 = Enable Slave Interface. (This bit must also be set for
ARP offload)
S S R
LAVE TATUS EGISTER
Description
–
• 1 = Source of SMBus attention is slave read cycle that
matched the SMB Slave address.
This bit is only set by hardware and can be reset by writing
a 1 to this position. Slave interface stretches the clock until
this bit is cleared.
Read request for ARP will not trigger this bit. ARP hardware
will supply read data in wire speed.
• 1 = Source of SMBus attention is completion of a slave
cycle that matched the SMB Slave address.
This bit is only set by hardware and can be reset by writing
a 1 to this position.
Completion for ARP will not trigger this bit. ARP Status
register contains that information.
• 0 = SMBus Controller slave interface is not processing
data.
• 1 = Indicates that the SMBus Controller slave interface is
in the process of receiving data. None of the other SMBus
Slave registers should be accessed if this bit is set.
Note: This bit is also set during ARP process.
Bro adco m C orp or atio n
R (O
EGISTER FFSET
(O 0 6C54)
FFSET X
Programmer's Guide
10/15/07
0 6C50)
X
Init Access
0 R/W
0 R/W
0 R/W
Init Access
0 R/W
0 R/W
0 R/W
0 RO
Document 5722-PG101-R