Table 397: Nvm Write Register (Offset 0X7008); Table 398: Nvm Address Register (Offset 0X700C); Table 399: Nvm Read Register (Offset 0X7010) - Broadcom BCM5722 Programmer's Manual

BCM5722
NVM W R
RITE EGISTER
Bit Field
31:0 wrdata
NVM A R
DDRESS EGISTER
Bit Field
31:24 Reserved
23:0 wraddr
NVM R R
EAD EGISTER
Bit Field
31:0 rddata
Page 371 Non-Volatile Memory Interface Registers
(O 0 7008)
FFSET X

Table 397: NVM Write Register (Offset 0x7008)

Description
32 bits of write data are used when write commands are executed.
For BCM5787, BCM5787M, BCM5754, and BCM5754M, when
bitbang_mode is set, bits 0 to 3 control the drive value of the SCK,
CS_L, SO, and SI pins respectively.
For BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757 in a
144-pin FBGA package, when bitbang_mode is set, bits 0 to 5 control
the drive value of the SCL, SDA, SDK, CS_L, SO, and SI pins
respectively. For a 100-pin FBGA package, the EECLK and EEDATA
share with SCK and SO.
(O 0 700C)
FFSET X

Table 398: NVM Address Register (Offset 0x700C)

Description
–
24-bit address value.
For BCM5787, BCM5787M, BCM5754, and BCM5754M,
when bitbang_mode is set, bits 0 to 3 control the OE value of
the SCK, CS_L, SO, and SI pins respectively. Note that SCL,
SDA, and SI are active high, and SCK, CS_L and SO are
active low.
For BCM5722, BCM5755, BCM5755M, BCM5756M,
BCM5757 in a 144-pin FBGA package, when bitbang_mode
is set, bits 0 to 5 control the OE value of the SCL, SDA, SDK,
CS_L, SO, and SI pins respectively. For a 100-pin FBGA
package, the EECLK and EEDATA share with SCK and SO.
SCL and SDA are active high, and SCK, CS_L, SO, and SI
are active low.
(O 0 7010)
FFSET X

Table 399: NVM Read Register (Offset 0x7010)

Description
32 bits of read data are used when read commands are executed.
For BCM5787, BCM5787M, BCM5754, and BCM5754M, when
bitbang_mode is set, bits 0 to 3 reflect the current input value of the
SCK, CS_L, SO, and SI pins, respectively.
For BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757 in a
144-pin FBGA package, when bitbang_mode is set, bits 0 to 5 control
the OE value of the SCL, SDA, SDK, CS_L, SO, and SI pins
respectively. For a 100-pin FBGA package, the EECLK and EEDATA
share with SCK and SO.
Bro adco m C orp or atio n
Programmer's Guide
10/15/07
Init Access
0 R/W
Init Access
0 RO
0 R/W
Init Access
0 R/W
Document 5722-PG101-R