Phy Auto-Negotiation; Register Quick Cross Reference; Integrated Phys; Table 89: Phy Flow Control Registers - Broadcom BCM5722 Programmer's Manual

BCM5722

PHY Auto-Negotiation

The PHY encodes flow control capability into Fast Link Pulse (FLPs) bursts. Link partners will extract encoded flow control
capability from FLPs and then create a Link Code Word (LCW). The LCW is a message, which contains a selector and
technology ability field. The technology ability field contains a bit called Pause_Operation_for Full_Duplex_Link (A5). Refer
to Annex 28-B of the IEEE 802.3 specifications. The A5 bit signifies that a link partner has implemented pause functionality.
If both link partners support auto-negotiation, they will further exchange data regarding flow control, using the next page bit
in the LCW.
Auto-advertise is integrally tied to auto-negotiation. If link partner does not support pause functionality, the PHY
Auto_Negotation_Link_Partner_Ability_Register does not set the Pause_Capable bit. The BCM5722 Ethernet controller
should not send pause frames to this link partner since flow control is not implemented or disabled. The BCM5722 Ethernet
controller can still accept pause frames, but sending a pause frame does not yield a preferred result.
R Q C
EGISTER UICK ROSS

Integrated PHYs

Table 89 lists the flow control registers in the integrated PHYs.
MDI Register Bit(s) Name
MII_status Link_Status
MII_auxiliary_status Auto_Negotation_HCD
Auto-negotiation Asymetric_Pause
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Pause_Capable
Auto-negotiation Link Asymetric_Pause
Partner Ability
Pause_Capable
Page 173 Flow Control
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EFERENCE

Table 89: PHY Flow Control Registers

Description
Link Pass State which indicates if a
valid link has been established.
Current operating mode and speed
Advertise to link partner, that
asymmetric pause is desired. This bit
works in conjunction with
Pause_Capable bit.
The pause capable bit indicates
whether half/full-duplex pause is
advertised.
Link Partner capability—the partner
desires asymmetric pause.
Link partner capability—the partner is
capable of full or half-duplex pause.
Bro adco m C orp or atio n
Programmer's Guide
Cross Reference
"MII Status Register (PHY_Addr =
0x1, Reg_Addr = 01h)" on
page 416.
"Auxiliary Status Summary
Register (PHY_Addr = 0x1,
Reg_Addr = 19h)" on page
"Auto-Negotiation Advertisement
Register (PHY_Addr = 0x1,
Reg_Addr = 04h)" on page
"Auto-Negotiation Link Partner
Ability Register (PHY_Addr = 0x1,
Reg_Addr = 05h)" on page
Document 5722-PG101-R
10/15/07
450.
419.
421.