Broadcom BCM5722 Programmer's Manual page 455

Programmer's Guide
10/15/07
Bit Field
19 Enable Pending
Completion Packet
Issue Fix CQ10452
18 PLL REFSEL Switch
Control CQ11011
17 Reserved
16 Power Management
Control
15 Power Down SerDes
Transmitter
14 Power Down SerDes
PLL
13 Power Down SerDes
Receiver
12 Enable Beacon
11 Automatic Timer
Threshold Enable
10 Enable DLLP Timeout
Mechanism
9 Check Receive Flow
Control Credits
8 Link Enable
7:0 Power Management
Control
Document 5722-PG101-R
Table 439: Data Link Control Register (Offset 0x7D00) (Cont.)
Description
Enable this fix to wake up from L1 and flush out pending
TLP.
• 1 = Disable fix
• 0 = Enable fix
Enable this fix to allow PLL source clock to switch to local
crystal at the absence of PCIe ref clock.
• 1 = Enable switch
• 0 = Disable switch
–
Enable power management clock switching (allows core
clk to be automatically muxed into PCIe clocks).
Forces the SerDes transmitter into the low-power state
(when cleared, the transmitter power state is controlled
by the power management state machine).
Forces the SerDes PLL into the low-power state (when
cleared, the PLL power state is controlled by the power
management state machine).
Forces the SerDes receiver into the low-power state
(when cleared, receiver power state is controlled by
power management state machine).
Enable transmission of In-band Beacon signal when
waking system.
• 1 = Enable automatic calculation of ACK Latency and
Replay Timeout Values.
• 0 = Use register values for ACK Latency and Replay
Timeout.
When set to 1, link is retrained if the DLLP receive timer
expires without receiving a valid DLLP.
Check receive flow control credit consumption and report
receive overflow errors when enabled.
Enable the data link layer functions.
These bits enable automatic power management
functions (power up/down or clock gating):
• 7 = Enable Active State power management.
• 6 = Enable PCI-PM power management (clearing this
bit does not disable PM_PME message generation).
• 5 = Enable SerDes transmitter power management.
• 4 = Enable SerDes PLL power management.
• 3 = Enable SerDes receiver power management.
• 2 = Enable transaction layer power management
(clock gating).
• 1 = Enable data link layer power management (clock
gating).
• 0 = Enable physical layer power management (clock
gating).
Bro adco m Co rp or atio n
BCM5722
Init Access
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
0xFF R/W
PCIe Registers Page 396