Table 466: Phy/Link Training N_Fts (Offset 0X7E14); Table 467: Phy Attention Register (Offset 0X7E18) - Broadcom BCM5722 Programmer's Manual

BCM5722
PHY/L T
INK RAINING
Bit Field
31:16 Reserved
Increase_TX_L0s_exit
(BCM5906 only)
Reserved (all others)
15:8 Inbound N_FTS
7:0 Outbound N_FTS
PHY A R
TTENTION EGISTER
Bit Field
31:8 Reserved
7 Hot reset
6 Link down
5 Training error
4 Buffer overrun
3 Buffer underrun
2 Receive framing error
1 Receive disparity error Receive 8b/10b running disparity error. Set when 8b10b
0 Receive code error
Page 407 PCIe Registers
N_FTS (O 0
FFSET X

Table 466: PHY/Link Training N_FTS (Offset 0x7E14)

Description
–
Add programmable register to increase tx L0s exit
latency. This may be used to offset the extended tx idle/
active time in the LP version of the SerDes Analog.
—
Inbound Maximum number of FTS ordered sets to be
sent when transitioning from L0s to L0 to achieve bit and
framing synchronization.
Outbound Maximum number of FTS ordered sets to be
sent when transitioning from L0s to L0 to achieve bit and
framing synchronization.
(O 0 7E18)
FFSET X

Table 467: PHY Attention Register (Offset 0x7E18)

Description
–
Hot reset event. Set by hot reset and cleared by explicitly
writing 1.
Link down event. When link status transitions from up to
down, this event bit will be set.
LTSSM training error.
Receive elastic buffer overrun.
Receive elastic buffer underrun.
Receive framing error. Set when receive framing error
count exceeds its threshold.
disparity count exceeds its threshold.
Receive 8b/10b code error. Set when 8b/10b error count
exceeds its threshold.
Bro adco m C orp or atio n
7E14)
Programmer's Guide
10/15/07
Init Access
0 RO
0 R/W
0 RO
0xFF RO
0x40 R/W
Init Access
0 RO
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
0 W2C
Document 5722-PG101-R