Table 378: Smbus Driver Select Register (Offset 0X6C24); Table 379: Asf Rng Command Register (0X6C30); Table 380: Asf Rng Data Register (0X6C34) - Broadcom BCM5722 Programmer's Manual

BCM5722
SMB D S
US RIVER ELECT
Bit Field
31: 1 Reserved
0 Driver Select
ASF RNG C
OMMAND
Bit Field
31:28 DB Reg Addr
27:8 Warm Ini
7 Warm Done
6 Rnd Vld
5 Upd Rnd
4 Attn Msk
3 Div2
2 Load Ini
1 Rnd En
0 Rnd Rst
ASF RNG D R
ATA EGISTER
Bit Field
31:0 Rnd32bit
Page 361 ASF Support Registers
R (O
EGISTER FFSET

Table 378: SMBus Driver Select Register (Offset 0x6C24)

Description
–
Set to 1 to enable SM_DATA_OUT and SM_CLK_OUT to
use new SMBus interface.
R (0 6C30)
EGISTER X

Table 379: ASF RNG Command Register (0x6c30)

Description
Debug register address. SW should always write 0 to this
field, other values are reserved for HW debug purpose.
Warm-up timer initial value. Used by the random
generator. SW should always write 0 to this field, other
values will cause a premature Warm Done (bit 7) to be set.
The random generator initialization is complete. It normally
(depends on the Warm Ini value) takes 2^21 core clocks
from setting load Ini (bit 2) to complete the initialization.
The 32-bit random number in ASF RNG Data Register (at
offset 0X6C34) is ready. Clear this bit by writing 1 to Upd
Rnd (bit 5).
Update the 32-bit random data. Writing 1 to this bit triggers
the random generator to start generating a new 32-bit
random number. Self Clear bit.
Attention Mask. Writing 1 to this bit disables the attention
signaling when Rnd Vld (bit 6) is set.
Divide. When configured low, the random number
generation is twice as fast as high.
Load Warm up timer initial value. Writing 1 to this bit clears
the Warm Done (bit 7) and the internal initialization timer
starts incrementing based on the Warm Ini (bit 27:8) value
until the Warm Done is set.
Random generator enable.
Random generator reset.
(0 6C34)
X

Table 380: ASF RNG Data Register (0x6C34)

Description
32-bit random number.
Bro adco m C orp or atio n
0 6C24)
X
Programmer's Guide
10/15/07
Init Access
RO
0 R/W
Init Access
0 R/W
0 R/W
0 RO
0 RO
0 R/W
0 R/W
0 R/W
0 W2C
0 R/W
0 W2C
Init Access
0 R
Document 5722-PG101-R