Broadcom NetXtreme/NetLink BCM5717 Manuals

Manuals and User Guides for Broadcom NetXtreme/NetLink BCM5717. We have 1 Broadcom NetXtreme/NetLink BCM5717 manual available for free PDF download: Programmer's Manual

Broadcom NetXtreme/NetLink BCM5717 Programmer's Manual (593 pages)

Brand: Broadcom | Category: Controller | Size: 3 MB

Table of Contents
12
About this Document

44
- Acronyms and Abbreviations
  44
- Document Conventions
  44
- Purpose and Audience
  44
- Table 1: Register Access Methods
  44
- References
  45
Technical Support

46
Section 1: Introduction

47
- Product Features
  
  47
  - Table 2: BCM5718 Family Product Features
    47
- Revision Levels
  
  49
  - Table 3: Family Revision Levels
    49
- Programming the Ethernet Controllers
  
  50
Section 2: Hardware Architecture

51
- Theory of Operation
  
  51
  - Figure 1: Individual Port Functional Block Diagram
    51
- Overview of Features
  
  52
  - Figure 2: High-Level System Functional Block Diagram
    53
- Receive Data Path
  
  54
  - RX Engine
    54
  - Rx Fifo
    54
  - Figure 3: Receive Data Path
    54
  - Rules Checker
    55
  - RX List Initiator
    55
- Transmit Data Path
  
  56
  - Tx Mac
    56
  - Tx Fifo
    56
  - Figure 4: Transmit Data Path
    56
- DMA Read
  
  57
  - Read Engine
    57
  - Read FIFO
    57
  - Figure 5: DMA Read Engine
    57
  - Buffer Manager
    58
- DMA Write
  
  58
  - Write Engine
    58
  - Write FIFO
    58
  - Figure 6: DMA Write Engine
    58
  - Buffer Manager
    59
- LED Control
  
  59
- Memory Arbiter
  
  59
- Host Coalescing
  
  60
  - Host Coalescing Engine
    60
  - Figure 7: Host Coalescing Engine
    60
  - Msi Fifo
    61
  - Status Block
    61
- PHY Control
  
  62
  - MII Block
    62
  - Figure 8: Media Independent Interface
    63
  - GMII Block
    64
  - Figure 9: GMII Block
    65
  - MDIO Register Interface
    66
    
    Figure 10: MDI Register Interface
    66
    
    Management Data Clock
    66
    
    Management Data Input/Output
    66
    
    Management Data Interrupt
    66
    
    Management Register Block
    66
- 10Bt/100Btx/1000Base-T Transceiver
  
  62
  - Auto-Negotiation
    62
  - Automatic MDI Crossover
    62
Section 3: NVRAM Configuration

67
- Overview
  
  67
- Self-Boot
  
  68
Section 4: Common Data Structures

69
Section 5: Receive Data Flow

88
- Introduction
  
  88
  - Figure 14: Receive Buffer Descriptor Cycle
    89
- Receive Producer Ring
  
  90
- Receive Return Rings
  
  93
- Checksum Calculation
  
  98
- VLAN Tag Strip
  
  98
  - Figure 16: Class of Service Example
    98
  - Table 25: Frame Format with 802.1Q VLAN Tag Inserted
    99
- RX Data Flow Diagram
  
  100
  - Figure 17: Overview Diagram of RX Flow
    100
- Receive Side Scaling
  
  101
  - Overview
    101
  - Functional Description
    101
  - RSS Parameters
    102
    
    Figure 18: RSS Receive Processing Sequence
    102
    
    Hash Function
    102
    
    Hash Mask
    102
    
    Hash Type
    102
    
    Indirection Table
    103
    
    Secret Hash Key
    103
  - RSS Initialization
    103
  - RSS Rx Packet Flow
    104
Section 6: Transmit Data Flow

105
- Introduction
  
  105
- Send Rings
  
  105
  - Figure 19: Relationships between All Components of a Send Ring
    106
    
    Figure 20: Max_Len Field in Ring Control Block
    107
    
    Ring Control Block
    107
    
    Figure 21: Relationship between Send Buffer Descriptors
    108
    
    Host-Based Send Ring
    108
- Checksum Offload
  
  109
- Large Segment Offload
  
  110
  - Quickstart
    110
  - LSO-Related Hardware Control Bits
    111
  - Table 26: Send Data Initiator Mode Register (Offset: 0Xc00)
    111
  - Table 27: ISO Send Data Initiator Mode Register (Offset: 0Xd00)
    111
  - Table 28: Read DMA Mode Register (Offset: 0X4800)
    111
  - Table 29: ISO Read DMA Mode Register (Offset: 0X4A00)
    111
  - Send Buffer Descriptor
    112
    
    Figure 22: Send Buffer Descriptor
    112
    
    Hdrlen[7:0]
    112
    
    Host Address
    112
    
    Length[15:0]
    112
    
    VLAN Tag[15:0]
    112
    
    Flags
    113
    
    Mss[13:0]
    113
    
    Table 30: Flag Field Description
    113
  - LSO Limitations
    114
  - Additional LSO Notes
    114
    
    Example TCP-Segmentation-Related (LSO) Register Values
    115
- Jumbo Frames
  
  116
  - Affected Data Structures
    117
    
    Extended RX Buffer Descriptor (BD)
    117
    
    Figure 23: Extended RX Buffer Descriptor
    118
    
    Table 31: Receive BD Error Flags
    119
    
    Receive Jumbo Producer Ring
    120
    
    Table 32: Receive BD Flags
    120
    
    Figure 24: Ring Control Block
    121
    
    Ring Control Blocks
    121
    
    Receive Return Ring(S)
    122
    
    Send Buffer Descriptor
    122
    
    Table 33: Receive BD Flags
    122
    
    Figure 25: Send Buffer Descriptor
    123
    
    Table 34: Send Buffer Descriptor Flags
    123
    
    Status Block
    124
    
    Table 35: Status Block
    124
    
    Misc BD Memory
    125
  - Device Driver Interface
    125
    
    Send Interface
    125
    
    Figure 26: Send Driver Interface
    126
    
    Receive Interface
    126
    
    Figure 27: Receive Producer Interface
    127
    
    Figure 28: Receive Return Interface
    128
    
    Large Segment Offload (LSO/TSO)
    128
  - Summary of Register Settings to Support Jumbo Frames
    129
- Scatter/Gather
  
  130
  - Figure 29: Scatter Gather of Frame Fragments
    130
- VLAN Tag Insertion
  
  131
- TX Data Flow Diagram
  
  131
  - Figure 30: Transmit Data Flow
    132
  - Figure 31: Basic Driver Flow to Send a Packet
    133
- Reset
  
  134
- MAC Address Setup/Configuration
  
  135
- Packet Filtering
  
  135
  - Multicast Hash Table Setup/Configuration
    135
  - Table 36: Mac Address Registers
    135
  - Ethernet CRC Calculation
    136
  - Generating CRC
    136
  - Checking CRC
    136
  - Initializing the MAC Hash Registers
    136
  - Table 37: Multicast Hash Table Registers
    137
  - Promiscuous Mode Setup/Configuration
    138
  - Broadcast Setup/Configuration
    138
Section 7: Device Control

139
Section 8: IEEE1588

152
Section 9: PCI

168
Section 10: Ethernet Link Configuration

203
- Overview
  
  203
- Gmii/MII
  
  203
- MDI Register Access
  
  210
  - Operational Characteristics
    210
  - Access Method
    211
    
    Auto-Access Method
    211
- Wake on LAN Mode/Low-Power
  
  212
- Flow Control
  
  223
  - Description
    223
  - Operational Characteristics
    223
    
    Transmit MAC
    223
    
    Receive MAC
    224
    
    Table 83: Transmit MAC Watermark Recommendation
    224
    
    Table 84: Pause Quanta
    224
    
    Table 85: Keep_Pause Recommended Value
    224
    
    Statistics Block
    225
    
    Table 86: Statistic Block
    225
    
    Integrated Macs
    226
    
    PHY Auto-Negotiation
    226
    
    Table 87: Integrated MAC Flow Control Registers
    226
  - Flow Control Initialization Pseudocode
    227
Section 11: Interrupt Processing

229
Section 12: IO Virtualization (IOV)

263
- Data Structure and Register Changes for IOV
  
  264
  - Mail Box Register Changes
    264
  - Receive Mail Box Register Changes
    264
  - Send Mail Box Register Changes
    264
  - Ring Control Block Changes
    264
  - VRQ Statistics
    264
  - MSI-X Vectors Changes
    265
  - Register Changes
    265
- IOV - Receive Side
  
  266
- IOV - Transmit Side
  
  267
  - Figure 53: IOV Receive Flow
    267
Section 13: Ethernet Controller Register Definitions

269
Section 14: Transceiver Registers

495
Appendix A: Flow Control

574
- Notes
  
  574
- Flow Control Scenario
  
  574
- Pause Control Frame
  
  578
  - Figure 61: File Transfer Scenario: File Transfer Complete
    578
  - Figure 62: Pause Control Frame
    578
Appendix B: Terminology

579
- Table 156: Terminology
  579
Appendix C: Device Register and Memory Map

580
- BCM5717 / BCM5718 Memory Map
  
  580
  - Table 157: BCM5717 / BCM5718 Memory Map
    580
- BCM5717 / BCM5718 Register Map
  
  583
  - Table 158: BCM5717 / BCM5718 Register Map
    583
- BCM5719 Memory Map
  
  585
  - Table 159: BCM5719 Memory Map
    585
- BCM5719 Register Map
  
  587
  - Table 160: BCM5719 Register Map
    587
- BCM5720 Memory Map
  
  589
  - Table 161: BCM5720 Memory Map
    589
- BCM5720 Register Map
  
  590
  - Table 162: BCM5720 Register Map
    590

Broadcom Categories

PCI Card Motherboard Adapter Computer Hardware Control Unit

More Broadcom Manuals

Broadcom NetXtreme/NetLink BCM5717 Manuals

Broadcom NetXtreme/NetLink BCM5717 Programmer's Manual (593 pages)

Table of Contents

About this Document

Technical Support

Section 1: Introduction

Product Features

Revision Levels

Programming the Ethernet Controllers

Section 2: Hardware Architecture

Theory of Operation

Overview of Features

Receive Data Path

Transmit Data Path

DMA Read

DMA Write

LED Control

Memory Arbiter

Host Coalescing

PHY Control

10Bt/100Btx/1000Base-T Transceiver

Section 3: NVRAM Configuration

Overview

Self-Boot

Section 4: Common Data Structures

Theory of Operation

Descriptor Rings

Status Block

Section 5: Receive Data Flow

Introduction

Receive Producer Ring

Receive Return Rings

Checksum Calculation

VLAN Tag Strip

RX Data Flow Diagram

Receive Side Scaling

Section 6: Transmit Data Flow

Introduction

Send Rings

Checksum Offload

Large Segment Offload

Jumbo Frames

Scatter/Gather

VLAN Tag Insertion

TX Data Flow Diagram

Reset

MAC Address Setup/Configuration

Packet Filtering

Section 7: Device Control

Initialization Procedure

Device Reset Procedure

Device Closing Procedure

Energy Efficient Ethernet

Section 8: IEEE1588

IEEE1588 Time Sync Introduction

Netxtreme Time Sync Assist

Hardware Description

EAV Reference Corrector

Transmit Time Stamping Service

Receive Time Stamp and Sequence ID Registers

Time Sync Registers

Section 9: PCI

Configuration Space

Bus Interface

Expansion ROM

Power Management

Endian Control (Byte and Word Swapping)

Section 10: Ethernet Link Configuration

Overview

Gmii/MII

MDI Register Access

Wake on LAN Mode/Low-Power

Flow Control

Section 11: Interrupt Processing

Netxtreme Legacy Interrupt Model

Basic Driver Interrupt Processing Flow

Host Coalescing

Msi

Msi-X

MSI-X Plumbing