Table 98: Class Code Register (Offset 0X09); Table 99: Cache Line Size Register (Offset 0X0C); Table 100: Latency Timer Register (Offset 0X0D); Table 101: Header Type Register (Offset 0X0E) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
C C R
LASS ODE EGISTER
The 24-bit Class Code register identifies the generic function of the device. All of the legal values are specific in the PCI
specification. This field is hardwired to the class code for an Ethernet interface (0x020000).
Bit Field
23:0 Class Code
C L S R
ACHE INE IZE
This register does not apply in PCIe systems and is implemented as a read-write field for legacy compatibility purposes only.
It has no impact on any PCIe device functionality.
Bit Field
7:0 Reserved
L T R
ATENCY IMER EGISTER
This register does not apply in PCIe systems.
Bit Field
7:0 Reserved
H T R
EADER YPE EGISTER
The 8-bit Header Type register identifies the layout of bytes 10h through 3Fh of the Configuration space, as well as whether
this adapter contains multiple functions. This register is always 0x00, which indicates a single function device (Type 0) using
the format specified in the PCI specification.
Bit Field
7:0 Header Type
Document 5722-PG101-R
(O 0 09)
FFSET X

Table 98: Class Code Register (Offset 0x09)

Description
PCI class code for this device.
(O 0
EGISTER FFSET

Table 99: Cache Line Size Register (Offset 0x0C)

Description
–
(O 0
FFSET X

Table 100: Latency Timer Register (Offset 0x0D)

Description
–
(O 0 0E)
FFSET X

Table 101: Header Type Register (Offset 0x0E)

Description
Identifies this device as having a single function.
Bro adco m Co rp or atio n
0C)
X
0D)
BCM5722
Init Access
020000h
Init Access
0 R/W
Init Access
0000h RO
Init Access
0 RO
PCI Configuration Registers
RO
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