Table 114: Power Management Control/Status Register (Offset 0X4C) - Broadcom BCM5722 Programmer's Manual

Programmer's Guide
10/15/07
Table 113: Power Management Capabilities Register (Offset 0x4A) (Cont.)
Bit Field
8:6 Aux Current
5 DSI
4 Reserved
3 PME Clock
2:0 Version
P M
OWER ANAGEMENT
This 16-bit register is used to manage the device's power management state as well as to enable and monitor PME events.

Table 114: Power Management Control/Status Register (Offset 0x4C)

Bit Field
15 PME Status
14:13 Data Scale
12:9 Data Select
8 PME Enable
7:2 Reserved
1:0 Power State
PMCSR-BSE R
EGISTER
The PMCSR_BSE (PMCSR PCI to PCI Bridge Support Extensions) register is not implemented in the device.
Document 5722-PG101-R
Description
The device supports the Data Register for reporting Aux
Current requirements so this field is not applicable.
Indicates that the device requires device specific
initialization (beyond the PCI configuration header) before
the generic class device driver is able to use it. This device
hardwires this bit to 0 to indicate that DSI is not necessary.
–
Indicates that the device relies on the presence of the PCI
clock for PME operation. The device does not require the
PCI clock to generate PME, therefore, this bit is hardwired to
0.
A value of 010b indicates that this function complies with
revision 1.1 of the PCI Power Management Interface Spec.
The device hardwires this value to 010.
C /S R
ONTROL TATUS
Description
This bit is set when the device would normally assert the PME
signal independent of the state of the PME Enable bit.
Writing a 1 to this bit will clear it and cause the device to stop
asserting PME (if enabled).
Indicates the scaling factor that is used when interpreting the
value of the Data register (offset 7 in PM capability space).
The device hardwires this value to 1 to indicate a scale of 1x.
Indicates which data is to be reported via the Data register
(offset 7 in PM capability space).
Enables the device to generate PME when this bit is set to 1.
When 0, PME generation is disabled.
–
Indicates the current power state of the device when read.
When written, it sets the device into the specified power state.
• 00 = D0
• 01 = D1
• 02 = D2
• 03 = D3
If software attempts to write an unsupported, optional state to
this field, the write operation must complete on the bus;
however, the data is discarded and no state change occurs.
(O 0 4E)
FFSET X
Bro adco m Co rp or atio n
(O 0
EGISTER FFSET
PCI Power Management Capabilities
BCM5722
Init
000
0
0
0
010
4C)
X
Init
0
1
0h
1 if VAux is
Present
00h
00
Access
RO
RO
RO
RO
RO
Access
R/W2C
RO
R/W
R/W
RO
R/W
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